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| Freescale Semiconductor, Inc. DSP56309 OVERVIEW SIGNAL/CONNECTION DESCRIPTIONS MEMORY CONFIGURATION CORE CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 A B C D I Freescale Semiconductor, Inc... GENERAL PURPOSE I/O HOST INTERFACE (HI08) ENHANCED SYNCHRONOUS SERIAL INTERFACE SERIAL COMMUNICATION INTERFACE (SCI) TIMER MODULE ON-CHIP EMULATION MODULE JTAG PORT BOOTSTRAP PROGRAM EQUATES BSDL LISTING PROGRAMMING REFERENCE INDEX For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 1 2 3 4 DSP56309 OVERVIEW SIGNAL/CONNECTION DESCRIPTIONS MEMORY CONFIGURATION CORE CONFIGURATION GENERAL PURPOSE I/O HOST INTERFACE (HI08) ENHANCED SYNCHRONOUS SERIAL INTERFACE SERIAL COMMUNICATION INTERFACE (SCI) TIMER MODULE ON-CHIP EMULATION MODULE JTAG PORT BOOTSTRAP PROGRAM EQUATES BSDL LISTING PROGRAMMING REFERENCE INDEX For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... 5 6 7 8 9 10 11 A B C D I Freescale Semiconductor, Inc. Rev. 0 DSP56309 Freescale Semiconductor, Inc... 24-Bit Digital Signal Processor UserOs Manual Motorola, Incorporated Semiconductor Products Sector DSP Division 6501 William Cannon Drive West Austin, TX 78735-8598 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. This document (and other documents) can be viewed on the World Wide Web at http://www.mot.com/SPS/DSP/documentation/ This manual is one of a set of three documents. You need the following manuals to have complete product information: Family Manual, UserOs Manual, and Technical Data. Freescale Semiconductor, Inc... OnCEa is a trademark of Motorola, Inc. IntelO is a registered trademark of the Intel Corporation. All other trademarks are those of their respective owners. a MOTOROLA INC., 1998 OReg. U.S. Pat. & Tm. Off. Order this document by DSP56309UM/D Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not authorized for use as components in life support devices or systems intended for surgical implant into the body or intended to support or sustain life. Buyer agrees to notify Motorola of any such intended end use whereupon Motorola shall determine availability and suitability of its product or are registered trademarks of products for the use intended. Motorola and Motorola, Inc. Motorola, Inc. is an Equal Employment Opportunity /Affirmative Action Employer. For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. TABLE OF CONTENTS SECTION 1 DSP56309 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.2 MANUAL ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 MANUAL CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.4 DSP56309 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.5 DSP56309 CORE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 1-7 1.5.1 General Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.5.2 Hardware Debugging Support . . . . . . . . . . . . . . . . . . . . . . 1-7 1.5.3 Reduced Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.6 DSP56300 CORE FUNCTIONAL BLOCKS . . . . . . . . . . . . . . 1-8 1.6.1 Data ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1.6.1.1 Data ALU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1.6.1.2 Multiplier-Accumulator (MAC) . . . . . . . . . . . . . . . . . . . . 1-9 1.6.2 Address Generation Unit (AGU) . . . . . . . . . . . . . . . . . . . . 1-9 1.6.3 Program Control Unit (PCU) . . . . . . . . . . . . . . . . . . . . . . 1-10 1.6.4 PLL and Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 1.6.5 JTAG TAP and OnCE Module . . . . . . . . . . . . . . . . . . . . . 1-11 1.6.6 On-Chip Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.6.7 Off-Chip Memory Expansion . . . . . . . . . . . . . . . . . . . . . . 1-12 1.7 INTERNAL BUSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.8 DSP56309 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . 1-14 1.9 DIRECT MEMORY ACCESS (DMA) . . . . . . . . . . . . . . . . . . 1-15 1.10 DSP56309 ARCHITECTURE OVERVIEW . . . . . . . . . . . . . 1-15 1.10.1 GPIO Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 1.10.2 Host Interface (HI08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 1.10.3 Enhanced Synchronous Serial Interface (ESSI) . . . . . . . 1-16 1.10.4 Serial Communications Interface (SCI) . . . . . . . . . . . . . . 1-16 1.10.5 Timer Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 SECTION 2 SIGNAL/CONNECTION DESCRIPTIONS. . . . . . . . 2-1 2.1 SIGNAL GROUPINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2 POWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Freescale Semiconductor, Inc... MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D iii Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... 2.3 2.4 2.5 2.6 2.6.1 2.6.2 2.6.3 2.7 2.8 2.8.1 2.8.2 2.9 2.9.1 2.9.2 2.10 2.11 2.12 GROUND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 PHASE-LOCKED LOOP (PLL) . . . . . . . . . . . . . . . . . . . . . . . 2-8 EXTERNAL MEMORY EXPANSION PORT (PORT A). . . . . 2-9 External Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 External Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 External Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 INTERRUPT AND MODE CONTROL . . . . . . . . . . . . . . . . . 2-14 HOST INTERFACE (HI08) . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Host Port Usage Considerations. . . . . . . . . . . . . . . . . . . 2-16 Host Port Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 ENHANCED SYNCHRONOUS SERIAL INTERFACE . . . . 2-24 ESSI0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 ESSI1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 SERIAL COMMUNICATION INTERFACE (SCI) . . . . . . . . . 2-32 TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33 ONCE/JTAG INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . 2-35 SECTION 3 MEMORY CONFIGURATION . . . . . . . . . . . . . . . . . 3-1 3.1 MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.1.1 Program Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.1.2 Data Memory Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.1.2.1 X Data Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.1.2.2 Y Data Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.1.3 Memory Space Configuration . . . . . . . . . . . . . . . . . . . . . . 3-5 3.2 RAM CONFIGURATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.2.1 On-Chip Program Memory (Program RAM) . . . . . . . . . . . 3-6 3.2.2 On-Chip X Data Memory (X Data RAM) . . . . . . . . . . . . . . 3-6 3.2.3 On-Chip Y Data Memory (Y Data RAM) . . . . . . . . . . . . . . 3-7 3.2.4 Bootstrap ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.3 MEMORY CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.3.1 Memory Space Configurations . . . . . . . . . . . . . . . . . . . . . 3-7 3.3.2 RAM Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.4 MEMORY MAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.5 INTERNAL I/O MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . 3-18 iv For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. SECTION 4 CORE CONFIGURATION . . . . . . . . . . . . . . . . . . . . 4-1 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.3 BOOTSTRAP PROGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.3.1 Mode 0: Expanded Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.3.2 Modes 1 to 7: Reserved. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.3.3 Mode 8: Expanded Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.3.4 Mode 9: Boot from Byte-Wide External Memory . . . . . . . . 4-7 4.3.5 Mode A: Boot from SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.3.6 Mode B: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.3.7 Modes C, D, E, F: Boot from HI08 . . . . . . . . . . . . . . . . . . . 4-8 4.3.7.1 Mode C: In ISA/DSP5630X Mode (8-Bit Bus) . . . . . . . 4-8 4.3.7.2 Mode D: In HC11 Non-multiplexed Mode . . . . . . . . . . 4-8 4.3.7.3 Mode E: In 8051 Multiplexed Bus Mode . . . . . . . . . . . 4-9 4.3.7.4 Mode F: In 68302/68360 Bus Mode . . . . . . . . . . . . . . . 4-9 4.4 INTERRUPT SOURCES AND PRIORITIES . . . . . . . . . . . . . 4-9 4.4.1 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.4.2 Interrupt Priority Levels . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.4.3 Interrupt Source Priorities Within an IPL . . . . . . . . . . . . . 4-14 4.5 DMA REQUEST SOURCES . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4.6 OPERATING MODE REGISTER (OMR) . . . . . . . . . . . . . . . 4-17 4.7 PLL CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 4.7.1 PCTL PLL Multiplication Factor Bits 011 . . . . . . . . . . . . 4-18 4.7.2 PCTL XTAL Disable Bit (XTLD) Bit 16. . . . . . . . . . . . . . . 4-18 4.7.3 PCTL Predivider Factor Bits (PD0PD3) Bits 2023. . . . 4-18 4.8 DEVICE IDENTIFICATION REGISTER (IDR) . . . . . . . . . . . 4-18 4.9 AA CONTROL REGISTERS (AAR0AAR3) . . . . . . . . . . . . 4-19 4.10 JTAG BOUNDARY SCAN REGISTER (BSR) . . . . . . . . . . . 4-20 SECTION 5 GENERAL-PURPOSE I/O . . . . . . . . . . . . . . . . . . . . 5-1 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2 PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2.1 Port B Signals and Registers. . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2.2 Port C Signals and Registers. . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2.3 Port D Signals and Registers. . . . . . . . . . . . . . . . . . . . . . . 5-4 5.2.4 Port E Signals and Registers. . . . . . . . . . . . . . . . . . . . . . . 5-4 Freescale Semiconductor, Inc... MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D v Freescale Semiconductor, Inc. 5.2.5 Triple Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 SECTION 6 HOST INTERFACE (HI08) . . . . . . . . . . . . . . . . . . . 6-1 6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.2 HI08 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.2.1 Host to DSP Core Interface. . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.2.2 HI08-to-Host Processor Interface . . . . . . . . . . . . . . . . . . . 6-4 6.3 HI08 HOST PORT SIGNALS. . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6.4 HI08 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6.5 HI08 DSP SIDE PROGRAMMEROS MODEL. . . . . . . . . . . . . 6-8 6.5.1 Host Receive Data Register (HRX). . . . . . . . . . . . . . . . . . 6-8 6.5.2 Host Transmit Data Register (HTX) . . . . . . . . . . . . . . . . . 6-9 6.5.3 Host Control Register (HCR). . . . . . . . . . . . . . . . . . . . . . . 6-9 6.5.3.1 HCR Host Receive Interrupt Enable (HRIE) Bit 0 . . . 6-10 6.5.3.2 HCR Host Transmit Interrupt Enable (HTIE) Bit 1 . . . 6-10 6.5.3.3 HCR Host Command Interrupt Enable (HCIE) Bit 2 . . 6-10 6.5.3.4 HCR Host Flags 2,3 (HF[3:2]) Bits 3, 4 . . . . . . . . . . . 6-10 6.5.3.5 HCR Reserved Bits 5-15 . . . . . . . . . . . . . . . . . . . . . . 6-10 6.5.4 Host Status Register (HSR) . . . . . . . . . . . . . . . . . . . . . . 6-11 6.5.4.1 HSR Host Receive Data Full (HRDF) Bit 0 . . . . . . . . 6-11 6.5.4.2 HSR Host Transmit Data Empty (HTDE) Bit 1 . . . . . . 6-11 6.5.4.3 HSR Host Command Pending (HCP) Bit 2 . . . . . . . . 6-11 6.5.4.4 HSR Host Flags 0, 1 (HF[1:0]) Bits 3, 4 . . . . . . . . . . . 6-11 6.5.4.5 HSR Reserved Bits 5-15 . . . . . . . . . . . . . . . . . . . . . . 6-11 6.5.5 Host Base Address Register (HBAR) . . . . . . . . . . . . . . . 6-12 6.5.5.1 HBAR Base Address (BA[10:3]) Bits 0-7 . . . . . . . . . . 6-12 6.5.5.2 HBAR Reserved Bits 8-15 . . . . . . . . . . . . . . . . . . . . . 6-12 6.5.6 Host Port Control Register (HPCR). . . . . . . . . . . . . . . . . 6-12 6.5.6.1 HPCR Host GPIO Port Enable (HGEN) Bit 0 . . . . . . . 6-13 6.5.6.2 HPCR Host Address Line 8 Enable (HA8EN) Bit 1 . . 6-13 6.5.6.3 HPCR Host Address Line 9 Enable (HA9EN) Bit 2 . . 6-13 6.5.6.4 HPCR Host Chip Select Enable (HCSEN) Bit 3 . . . . . 6-13 6.5.6.5 HPCR Host Request Enable (HREN) Bit 4 . . . . . . . . 6-14 6.5.6.6 HPCR Host Acknowledge Enable (HAEN) Bit 5. . . . . 6-14 6.5.6.7 HPCR Host Enable (HEN) Bit 6 . . . . . . . . . . . . . . . . . 6-14 6.5.6.8 HPCR Reserved Bit 7. . . . . . . . . . . . . . . . . . . . . . . . . 6-14 Freescale Semiconductor, Inc... vi For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. 6.5.6.9 HPCR Host Request Open Drain (HROD) Bit 8 . . . . . 6-14 6.5.6.10 HPCR Host Data Strobe Polarity (HDSP) Bit 9. . . . . . 6-14 6.5.6.11 HPCR Host Address Strobe Polarity (HASP) Bit 10 . . 6-15 6.5.6.12 HPCR Host Multiplexed Bus (HMUX) Bit 11 . . . . . . . . 6-15 6.5.6.13 HPCR Host Dual Data Strobe (HDDS) Bit 12 . . . . . . . 6-15 6.5.6.14 HPCR Host Chip Select Polarity (HCSP) Bit 13 . . . . . 6-16 6.5.6.15 HPCR Host Request Polarity (HRP) Bit 14 . . . . . . . . . 6-16 6.5.6.16 HPCR Host Acknowledge Polarity (HAP) Bit 15 . . . . . 6-16 6.5.7 Host Data Direction Register (HDDR) . . . . . . . . . . . . . . . 6-17 6.5.8 Host Data Register (HDR) . . . . . . . . . . . . . . . . . . . . . . . . 6-17 6.5.9 DSP Side Registers After Reset . . . . . . . . . . . . . . . . . . . 6-18 6.5.10 Host Interface DSP Core Interrupts . . . . . . . . . . . . . . . . . 6-19 6.6 HI08-EXTERNAL HOST PROGRAMMEROS MODEL . . . . . 6-20 6.6.1 Interface Control Register (ICR) . . . . . . . . . . . . . . . . . . . 6-22 6.6.1.1 ICR Receive Request Enable (RREQ) Bit 0 . . . . . . . . 6-23 6.6.1.2 ICR Transmit Request Enable (TREQ) Bit 1. . . . . . . . 6-23 6.6.1.3 ICR Double Host Request (HDRQ) Bit 2. . . . . . . . . . . 6-23 6.6.1.4 ICR Host Flag 0 (HF0) Bit 3 . . . . . . . . . . . . . . . . . . . . 6-24 6.6.1.5 ICR Host Flag 1 (HF1) Bit 4 . . . . . . . . . . . . . . . . . . . . 6-24 6.6.1.6 ICR Host Little Endian (HLEND) Bit 5 . . . . . . . . . . . . . 6-24 6.6.1.7 ICR Reserved Bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 6.6.1.8 ICR Initialize Bit (INIT) Bit 7 . . . . . . . . . . . . . . . . . . . . 6-24 6.6.2 Command Vector Register (CVR) . . . . . . . . . . . . . . . . . . 6-25 6.6.2.1 CVR Host Vector (HV[6:0]) Bits 06 . . . . . . . . . . . . . . 6-25 6.6.2.2 CVR Host Command Bit (HC) Bit 7. . . . . . . . . . . . . . . 6-26 6.6.3 Interface Status Register (ISR) . . . . . . . . . . . . . . . . . . . . 6-26 6.6.3.1 ISR Receive Data Register Full (RXDF) Bit 0 . . . . . . . 6-26 6.6.3.2 ISR Transmit Data Register Empty (TXDE) Bit 1 . . . . 6-27 6.6.3.3 ISR Transmitter Ready (TRDY) Bit 2 . . . . . . . . . . . . . 6-27 6.6.3.4 ISR Host Flag 2 (HF2) Bit 3 . . . . . . . . . . . . . . . . . . . . 6-27 6.6.3.5 ISR Host Flag 3 (HF3) Bit 4 . . . . . . . . . . . . . . . . . . . . 6-27 6.6.3.6 ISR Reserved Bits 5, 6 . . . . . . . . . . . . . . . . . . . . . . . . 6-27 6.6.3.7 ISR Host Request (HREQ) Bit 7 . . . . . . . . . . . . . . . . . 6-27 6.6.4 Interrupt Vector Register (IVR) . . . . . . . . . . . . . . . . . . . . 6-28 6.6.5 Receive Byte Registers (RXH: RXM: RXL) . . . . . . . . . . . 6-28 6.6.6 Transmit Byte Registers (TXH:TXM:TXL) . . . . . . . . . . . . 6-29 Freescale Semiconductor, Inc... MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D vii Freescale Semiconductor, Inc. 6.6.7 6.6.8 6.7 6.7.1 6.7.2 6.7.3 6.8 Host Side Registers After Reset . . . . . . . . . . . . . . . . . . . General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . SERVICING THE HOST INTERFACE . . . . . . . . . . . . . . . . HI08 Host Processor Data Transfer . . . . . . . . . . . . . . . . Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Servicing Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HI08 PROGRAMMING MODEL QUICK REFERENCE. . . . 7 6-30 6-30 6-31 6-31 6-31 6-32 6-34 SECTION ENHANCEDSYNCHRONOUSSERIALINTERFACE(ESSI) 7-1 7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.2 ENHANCEMENTS TO THE ESSI . . . . . . . . . . . . . . . . . . . . . 7-3 7.3 ESSI DATA AND CONTROL SIGNALS . . . . . . . . . . . . . . . . 7-4 7.3.1 Serial Transmit Data (STD) Signal . . . . . . . . . . . . . . . . . . 7-4 7.3.2 Serial Receive Data Signal (SRD) . . . . . . . . . . . . . . . . . . 7-4 7.3.3 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.3.4 Serial Control Signal (SC0) . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.3.5 Serial Control Signal (SC1) . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.3.6 Serial Control Signal (SC2) . . . . . . . . . . . . . . . . . . . . . . . . 7-8 7.4 ESSI PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . 7-8 7.4.1 ESSI Control Register A (CRA). . . . . . . . . . . . . . . . . . . . 7-11 7.4.1.1 CRA Prescale Modulus Select PM[7:0] Bits 70 . . . . 7-11 7.4.1.2 CRA Reserved Bits 810 . . . . . . . . . . . . . . . . . . . . . . 7-11 7.4.1.3 CRA Prescaler Range (PSR) Bit 11 . . . . . . . . . . . . . . 7-11 7.4.1.4 CRA Frame Rate Divider Control DC[4:0] Bits 1612 7-12 7.4.1.5 CRA Reserved Bit 17 . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 7.4.1.6 CRA Alignment Control (ALC) Bit 18 . . . . . . . . . . . . . 7-13 7.4.1.7 CRA Word-length Control (WL[2:0]) Bits 2119 . . . . . 7-14 7.4.1.8 CRA Select SC1 (SSC1) Bit 22 . . . . . . . . . . . . . . . . . 7-14 7.4.1.9 CRA Reserved Bit 23 . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 7.4.2 ESSI Control Register B (CRB). . . . . . . . . . . . . . . . . . . . 7-15 7.4.2.1 CRB Serial Output Flags (OF0, OF1) Bits 0, 1. . . . . . 7-15 7.4.2.1.1 CRB Serial Output Flag 0 (OF0) Bit 0 . . . . . . . . . . 7-15 7.4.2.1.2 CRB Serial Output Flag 1 (OF1) Bit 1 . . . . . . . . . . 7-16 7.4.2.2 CRB Serial Control Direction 0 (SCD0) Bit 2 . . . . . . . 7-16 7.4.2.3 CRB Serial Control Direction 1 (SCD1) Bit 3 . . . . . . . 7-16 Freescale Semiconductor, Inc... viii For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. 7.4.2.4 7.4.2.5 7.4.2.6 7.4.2.7 7.4.2.8 7.4.2.9 7.4.2.10 7.4.2.11 7.4.2.12 7.4.2.13 7.4.2.14 7.4.2.15 7.4.2.16 7.4.2.17 7.4.2.18 7.4.2.19 7.4.2.20 7.4.2.21 7.4.2.22 7.4.2.23 7.4.3 7.4.3.1 7.4.3.2 7.4.3.3 7.4.3.4 7.4.3.5 7.4.3.6 7.4.3.7 7.4.3.8 7.4.4 7.4.5 7.4.6 7.4.7 7.4.8 7.4.9 7.4.10 CRB Serial Control Direction 2 (SCD2) Bit 4 . . . . . . . 7-16 CRB Clock Source Direction (SCKD) Bit 5 . . . . . . . . . 7-16 CRB Shift Direction (SHFD) Bit 6 . . . . . . . . . . . . . . . . 7-17 CRB Frame Sync Length FSL[1:0] Bits 7 and 8 . . . . . 7-17 CRB Frame Sync Relative Timing (FSR) Bit 9 . . . . . . 7-17 CRB Frame Sync Polarity (FSP) Bit 10. . . . . . . . . . . . 7-17 CRB Clock Polarity (CKP) Bit 11. . . . . . . . . . . . . . . . . 7-18 CRB Synchronous /Asynchronous (SYN) Bit 12. . . . . 7-18 CRB ESSI Mode Select (MOD) Bit 13 . . . . . . . . . . . . 7-20 Enabling, Disabling ESSI Data Transmission . . . . . . . 7-22 CRB ESSI Transmit 2 Enable (TE2) Bit 14 . . . . . . . . . 7-22 CRB ESSI Transmit 1 Enable (TE1) Bit 15 . . . . . . . . . 7-23 CRB ESSI Transmit 0 Enable (TE0) Bit 16 . . . . . . . . . 7-24 CRB ESSI Receive Enable (RE) Bit 17. . . . . . . . . . . . 7-26 CRB ESSI Transmit Interrupt Enable (TIE) Bit 18. . . . 7-26 CRB ESSI Receive Interrupt Enable (RIE) Bit 19 . . . . 7-26 Transmit Last Slot Interrupt Enable (TLIE) Bit 20 . . . . 7-26 Receive Last Slot Interrupt Enable (RLIE) Bit 21 . . . . 7-27 Transmit Exception Interrupt Enable (TEIE) Bit 22 . . . 7-27 Receive Exception Interrupt Enable (REIE) Bit 23 . . . 7-27 ESSI Status Register (SSISR). . . . . . . . . . . . . . . . . . . . . 7-27 SSISR Serial Input Flag 0 (IF0) Bit 0 . . . . . . . . . . . . . 7-28 SSISR Serial Input Flag 1 (IF1) Bit 1 . . . . . . . . . . . . . 7-28 SSISR Transmit Frame Sync Flag (TFS) Bit 2 . . . . . . 7-28 SSISR Receive Frame Sync Flag (RFS) Bit 3 . . . . . . 7-28 SSISR Transmitter Underrun Error Flag (TUE) Bit 4 . 7-29 SSISR Receiver Overrun Error Flag (ROE) Bit 5 . . . . 7-29 ESSI Transmit Data Register Empty (TDE) Bit 6 . . . . 7-29 ESSI Receive Data Register Full (RDF) Bit 7 . . . . . . . 7-30 ESSI Receive Shift Register . . . . . . . . . . . . . . . . . . . . . . 7-33 ESSI Receive Data Register (RX) . . . . . . . . . . . . . . . . . . 7-33 ESSI Transmit Shift Registers . . . . . . . . . . . . . . . . . . . . . 7-33 ESSI Transmit Data Registers (TX0-2) . . . . . . . . . . . . . . 7-34 ESSI Time Slot Register (TSR) . . . . . . . . . . . . . . . . . . . . 7-34 Transmit Slot Mask Registers (TSMA, TSMB) . . . . . . . . 7-34 Receive Slot Mask Registers (RSMA, RSMB). . . . . . . . . 7-35 Freescale Semiconductor, Inc... MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D ix Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... 7.5 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.1 ESSI After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.2 ESSI Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.3 ESSI Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.4 Operating Modes: Normal, Network, and On-Demand . . 7.5.4.1 Normal/Network/On-Demand Mode Selection . . . . . . 7.5.4.2 Synchronous/Asynchronous Operating Modes . . . . . 7.5.4.3 Frame Sync Selection . . . . . . . . . . . . . . . . . . . . . . . . 7.5.4.3.1 Frame Sync Signal Format . . . . . . . . . . . . . . . . . . 7.5.4.3.2 Frame Sync Length for Multiple Devices . . . . . . . . 7.5.4.3.3 Word-Length Frame Sync and Data-Word Timing 7.5.4.3.4 Frame Sync Polarity . . . . . . . . . . . . . . . . . . . . . . . 7.5.4.4 Byte Format (LSB/MSB) for the Transmitter . . . . . . . 7.5.5 Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6 GPIO SIGNALS AND REGISTERS. . . . . . . . . . . . . . . . . . . 7.6.1 Port Control Register (PCR) . . . . . . . . . . . . . . . . . . . . . . 7.6.2 Port Direction Register (PRR) . . . . . . . . . . . . . . . . . . . . . 7.6.3 Port Data Register (PDR) . . . . . . . . . . . . . . . . . . . . . . . . 7-36 7-36 7-36 7-37 7-40 7-40 7-40 7-41 7-41 7-41 7-41 7-42 7-42 7-42 7-43 7-43 7-44 7-45 SECTION 8 SERIAL COMMUNICATION INTERFACE (SCI) . . 8-1 8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.2 SCI I/O SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.2.1 Receive Data (RXD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.2.2 Transmit Data (TXD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.2.3 SCI Serial Clock (SCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.3 SCI PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.3.1 SCI Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . 8-8 8.3.1.1 SCR Word Select (WDS[0:2]) Bits 02 . . . . . . . . . . . . 8-8 8.3.1.2 SCR SCI Shift Direction (SSFTD) Bit 3 . . . . . . . . . . . . 8-9 8.3.1.3 SCR Send Break (SBK) Bit 4 . . . . . . . . . . . . . . . . . . . . 8-9 8.3.1.4 SCR Wakeup Mode Select (WAKE) Bit 5 . . . . . . . . . . 8-9 8.3.1.5 SCR Receiver Wakeup Enable (RWU) Bit 6 . . . . . . . . 8-9 8.3.1.6 SCR Wired-OR Mode Select (WOMS) Bit 7. . . . . . . . 8-10 8.3.1.7 SCR Receiver Enable (RE) Bit 8 . . . . . . . . . . . . . . . . 8-10 8.3.1.8 SCR Transmitter Enable (TE) Bit 9 . . . . . . . . . . . . . . 8-10 8.3.1.9 SCR Idle Line Interrupt Enable (ILIE) Bit 10. . . . . . . . 8-11 x For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. 8.3.1.10 SCR SCI Receive Interrupt Enable (RIE) Bit 11 . . . . . 8-11 8.3.1.11 SCR SCI Transmit Interrupt Enable (TIE) Bit 12. . . . . 8-12 8.3.1.12 SCR Timer Interrupt Enable (TMIE) Bit 13 . . . . . . . . . 8-12 8.3.1.13 SCR Timer Interrupt Rate (STIR) Bit 14 . . . . . . . . . . . 8-12 8.3.1.14 SCR SCI Clock Polarity (SCKP) Bit 15 . . . . . . . . . . . . 8-12 8.3.1.15 Receive with Exception Interrupt Enable (REIE) Bit 168-13 8.3.2 SCI Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . . 8-13 8.3.2.1 SSR Transmitter Empty (TRNE) Bit 0 . . . . . . . . . . . . . 8-13 8.3.2.2 SSR Transmit Data Register Empty (TDRE) Bit 1 . . . 8-13 8.3.2.3 SSR Receive Data Register Full (RDRF) Bit 2 . . . . . . 8-14 8.3.2.4 SSR Idle Line Flag (IDLE) Bit 3. . . . . . . . . . . . . . . . . . 8-14 8.3.2.5 SSR Overrun Error Flag (OR) Bit 4. . . . . . . . . . . . . . . 8-14 8.3.2.6 SSR Parity Error (PE) Bit 5 . . . . . . . . . . . . . . . . . . . . . 8-14 8.3.2.7 SSR Framing Error Flag (FE) Bit 6 . . . . . . . . . . . . . . . 8-15 8.3.2.8 SSR Received Bit 8 (R8) Address Bit 7 . . . . . . . . . . . 8-15 8.3.3 SCI Clock Control Register (SCCR) . . . . . . . . . . . . . . . . 8-15 8.3.3.1 SCCR Clock Divider (CD[11:0]) Bits 110 . . . . . . . . . 8-16 8.3.3.2 SCCR Clock Out Divider (COD) Bit 12 . . . . . . . . . . . . 8-16 8.3.3.3 SCCR SCI Clock Prescaler (SCP) Bit 13 . . . . . . . . . . 8-17 8.3.3.4 SCCR Receive Clock Mode Source (RCM) Bit 14 . . . 8-17 8.3.3.5 SCCR Transmit Clock Source Bit (TCM) Bit 15 . . . . . 8-18 8.3.4 SCI Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 8.3.4.1 SCI Receive Registers (SRX) . . . . . . . . . . . . . . . . . . . 8-19 8.3.4.2 SCI Transmit Registers . . . . . . . . . . . . . . . . . . . . . . . . 8-20 8.4 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21 8.4.1 SCI After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22 8.4.2 SCI Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24 8.4.3 SCI Initialization Example . . . . . . . . . . . . . . . . . . . . . . . . 8-25 8.4.4 Preamble, Break, and Data Transmission Priority . . . . . . 8-26 8.4.5 SCI Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26 8.5 GPIO SIGNALS AND REGISTERS . . . . . . . . . . . . . . . . . . . 8-27 8.5.1 Port E Control Register (PCRE) . . . . . . . . . . . . . . . . . . . 8-27 8.5.2 Port E Direction Register (PRRE) . . . . . . . . . . . . . . . . . . 8-27 8.5.3 Port E Data Register (PDRE) . . . . . . . . . . . . . . . . . . . . . 8-28 Freescale Semiconductor, Inc... MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D xi Freescale Semiconductor, Inc. SECTION 9 TRIPLE TIMER MODULE . . . . . . . . . . . . . . . . . . . . 9-1 9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.2 TRIPLE TIMER MODULE ARCHITECTURE . . . . . . . . . . . . 9-3 9.2.1 Triple Timer Module Block Diagram . . . . . . . . . . . . . . . . . 9-3 9.2.2 Timer Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9.3 TRIPLE TIMER MODULE PROGRAMMING MODEL. . . . . . 9-5 9.3.1 Prescaler Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 9.3.2 Timer Prescaler Load Register (TPLR). . . . . . . . . . . . . . . 9-7 9.3.2.1 TPLR Prescaler Preload Value (PL[20:0]) Bits 20-0 . . 9-7 9.3.2.2 TPLR Prescaler Source (PS[1:0]) Bits 22-21 . . . . . . . . 9-7 9.3.2.3 TPLR Reserved Bit 23 . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.3.3 Timer Prescaler Count Register (TPCR). . . . . . . . . . . . . . 9-8 9.3.3.1 TPCR Prescaler Counter Value (PC[20:0]) Bits 20-0 . . 9-9 9.3.3.2 TPCR Reserved Bits 23-21 . . . . . . . . . . . . . . . . . . . . . 9-9 9.3.4 Timer Control/Status Register (TCSR) . . . . . . . . . . . . . . . 9-9 9.3.4.1 Timer Enable (TE) Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . 9-9 9.3.4.2 Timer Overflow Interrupt Enable (TOIE) Bit 1 . . . . . . . 9-9 9.3.4.3 Timer Compare Interrupt Enable (TCIE) Bit 2 . . . . . . 9-10 9.3.4.4 Timer Control (TC[3:0]) Bits 4-7 . . . . . . . . . . . . . . . . . 9-10 9.3.4.5 Inverter (INV) Bit 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 9.3.4.6 Timer Reload Mode (TRM) Bit 9 . . . . . . . . . . . . . . . . 9-13 9.3.4.7 Direction (DIR) Bit 11 . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 9.3.4.8 Data Input (DI) Bit 12 . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 9.3.4.9 Data Output (DO) Bit 13 . . . . . . . . . . . . . . . . . . . . . . . 9-14 9.3.4.10 Prescaler Clock Enable (PCE) Bit 15 . . . . . . . . . . . . . 9-14 9.3.4.11 Timer Overflow Flag (TOF) Bit 20 . . . . . . . . . . . . . . . 9-14 9.3.4.12 Timer Compare Flag (TCF) Bit 21 . . . . . . . . . . . . . . . 9-15 9.3.4.13 TCSR Reserved Bits 3, 10, 14, 16-19, 22, 23 . . . . . . 9-15 9.3.5 Timer Load Register (TLR) . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.3.6 Timer Compare Register (TCPR) . . . . . . . . . . . . . . . . . . 9-16 9.3.7 Timer Count Register (TCR) . . . . . . . . . . . . . . . . . . . . . . 9-16 9.4 TIMER OPERATIONAL MODES. . . . . . . . . . . . . . . . . . . . . 9-16 9.4.1 Timing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17 9.4.1.1 Timer GPIO (Mode 0) . . . . . . . . . . . . . . . . . . . . . . . . . 9-17 9.4.1.2 Timer Pulse (Mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 9.4.1.3 Timer Toggle (Mode 2) . . . . . . . . . . . . . . . . . . . . . . . . 9-19 Freescale Semiconductor, Inc... xii For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... 9.4.1.4 9.4.2 9.4.2.1 9.4.2.2 9.4.2.3 9.4.2.4 9.4.3 9.4.4 9.4.4.1 9.4.4.2 9.4.5 9.4.6 9.4.6.1 9.4.6.2 9.4.7 Timer Event Counter (Mode 3) . . . . . . . . . . . . . . . . . . 9-20 Signal Measurement Modes . . . . . . . . . . . . . . . . . . . . . . 9-20 Measurement Accuracy . . . . . . . . . . . . . . . . . . . . . . . 9-21 Measurement Input Width (Mode 4) . . . . . . . . . . . . . . 9-21 Measurement Input Period (Mode 5) . . . . . . . . . . . . . 9-22 Measurement Capture (Mode 6) . . . . . . . . . . . . . . . . . 9-23 Pulse Width Modulation (PWM, Mode 7). . . . . . . . . . . . . 9-24 Watchdog Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25 Watchdog Pulse (Mode 9). . . . . . . . . . . . . . . . . . . . . . 9-25 Watchdog Toggle (Mode 10). . . . . . . . . . . . . . . . . . . . 9-26 Reserved Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27 Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27 Timer Behavior during Wait. . . . . . . . . . . . . . . . . . . . . 9-27 Timer Behavior during Stop . . . . . . . . . . . . . . . . . . . . 9-27 DMA Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27 SECTION 10 ON-CHIP EMULATION MODULE . . . . . . . . . . . . . 10-1 10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.2 ONCE MODULE SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.3 DEBUG EVENT (DE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.4 ONCE CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.4.1 OnCE Command Register (OCR) . . . . . . . . . . . . . . . . . . 10-5 10.4.1.1 Register Select (RS4RS0) Bits 04 . . . . . . . . . . . . . 10-5 10.4.1.2 Exit Command (EX) Bit 5 . . . . . . . . . . . . . . . . . . . . . . 10-5 10.4.1.3 GO Command (GO) Bit 6 . . . . . . . . . . . . . . . . . . . . . . 10-6 10.4.1.4 Read/Write Command (R/W) Bit 7 . . . . . . . . . . . . . . . 10-6 10.4.2 OnCE Decoder (ODEC). . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 10.4.3 OnCE Status and Control Register (OSCR) . . . . . . . . . . 10-8 10.4.3.1 Trace Mode Enable (TME) Bit 0 . . . . . . . . . . . . . . . . . 10-8 10.4.3.2 Interrupt Mode Enable (IME) Bit 1. . . . . . . . . . . . . . . . 10-8 10.4.3.3 Software Debug Occurrence (SWO) Bit 2. . . . . . . . . . 10-8 10.4.3.4 Memory Breakpoint Occurrence (MBO) Bit 3 . . . . . . . 10-8 10.4.3.5 Trace Occurrence (TO) Bit 4. . . . . . . . . . . . . . . . . . . . 10-9 10.4.3.6 Reserved OCSR Bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 10.4.3.7 Core Status (OS0, OS1) Bits 6-7 . . . . . . . . . . . . . . . . 10-9 10.4.3.8 Reserved Bits 8-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D xiii Freescale Semiconductor, Inc. 10.5 ONCE MEMORY BREAKPOINT LOGIC. . . . . . . . . . . . . . . 10-9 10.5.1 OnCE Memory Address Latch (OMAL). . . . . . . . . . . . . 10-11 10.5.2 OnCE Memory Limit Register 0 (OMLR0). . . . . . . . . . . 10-11 10.5.3 OnCE Memory Address Comparator 0 (OMAC0) . . . . . 10-11 10.5.4 OnCE Memory Limit Register 1 (OMLR1). . . . . . . . . . . 10-11 10.5.5 OnCE Memory Address Comparator 1 (OMAC1) . . . . . 10-11 10.5.6 OnCE Breakpoint Control Register (OBCR) . . . . . . . . . 10-12 10.5.6.1 Memory Breakpoint Select (MBS0MBS1) . . . . . . . 10-12 10.5.6.2 Breakpoint 0 Read/Write Select (RW00RW01) . . . 10-12 10.5.6.3 Breakpoint 0 Condition Code Select (CC00CC01). 10-13 10.5.6.4 Breakpoint 1 Read/Write Select (RW10RW11) . . . 10-13 10.5.6.5 Breakpoint 1 Condition Code Select (CC10CC11). 10-14 10.5.6.6 Breakpoint 0 and 1 Event Select (BT0BT1) . . . . . . 10-14 10.5.6.7 OnCE Memory Breakpoint Counter (OMBC) . . . . . . 10-14 10.5.6.8 Reserved Bits 12-15 . . . . . . . . . . . . . . . . . . . . . . . . . 10-15 10.6 ONCE TRACE LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15 10.7 METHODS OF ENTERING DEBUG MODE . . . . . . . . . . . 10-16 10.7.1 External Debug Request During RESET Assertion . . . 10-16 10.7.2 External Debug Request During Normal Activity . . . . . 10-16 10.7.3 Executing the JTAG DEBUG_REQUEST Instruction . . 10-17 10.7.4 External Debug Request During Stop . . . . . . . . . . . . . . 10-17 10.7.5 External Debug Request During Wait . . . . . . . . . . . . . . 10-17 10.7.6 Software Request During Normal Activity . . . . . . . . . . . 10-18 10.7.7 Enabling Trace Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18 10.7.8 Enabling Memory Breakpoints . . . . . . . . . . . . . . . . . . . 10-18 10.8 PIPELINE INFORMATION AND OGDB REGISTER. . . . . 10-18 10.8.1 OnCE PDB Register (OPDBR) . . . . . . . . . . . . . . . . . . . 10-19 10.8.2 OnCE PIL Register (OPILR) . . . . . . . . . . . . . . . . . . . . . 10-19 10.8.3 OnCE GDB Register (OGDBR). . . . . . . . . . . . . . . . . . . 10-20 10.9 DEBUGGING RESOURCES . . . . . . . . . . . . . . . . . . . . . . . 10-20 10.9.1 OnCE PAB Register for Fetch (OPABFR) . . . . . . . . . . 10-20 10.9.2 PAB Register for Decode (OPABDR) . . . . . . . . . . . . . . 10-20 10.9.3 OnCE PAB Register for Execute (OPABEX) . . . . . . . . 10-20 10.9.4 Trace Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21 10.10 SERIAL PROTOCOL DESCRIPTION . . . . . . . . . . . . . . . . 10-22 10.11 TARGET SITE DEBUG SYSTEM REQUIREMENTS . . . . 10-23 Freescale Semiconductor, Inc... xiv For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... 10.12 ONCE MODULE EXAMPLES . . . . . . . . . . . . . . . . . . . . . . 10-23 10.12.1 Checking Whether the Chip Has Entered Debug Mode 10-24 10.12.2 Polling the JTAG Instruction Shift Register . . . . . . . . . . 10-24 10.12.3 Saving Pipeline Information . . . . . . . . . . . . . . . . . . . . . . 10-25 10.12.4 Reading the Trace Buffer. . . . . . . . . . . . . . . . . . . . . . . . 10-25 10.12.5 Displaying a Specified Register . . . . . . . . . . . . . . . . . . . 10-26 10.12.6 Displaying X Memory Area Starting at Address $xxxx . 10-26 10.12.7 Returning from Debug to Normal Mode (Same Program)10-28 10.12.8 Returning from Debug to Normal Mode (New Program) 10-28 10.13 JTAG PORT/ONCE MODULE INTERACTION . . . . . . . . . 10-29 SECTION 11 JTAG PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.2 JTAG SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.2.1 Test Clock (TCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.2.2 Test Mode Select (TMS) . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.2.3 Test Data Input (TDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.2.4 Test Data Output (TDO) . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.2.5 Test Reset (TRST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.3 TAP CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.3.1 Boundary Scan Register (BSR) . . . . . . . . . . . . . . . . . . . . 11-7 11.3.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 11.3.2.1 EXTEST (B[3:0] = 0000) . . . . . . . . . . . . . . . . . . . . . . . 11-8 11.3.2.2 SAMPLE/PRELOAD (B[3:0] = 0001). . . . . . . . . . . . . . 11-9 11.3.2.3 IDCODE (B[3:0] = 0010) . . . . . . . . . . . . . . . . . . . . . . . 11-9 11.3.2.4 CLAMP (B[3:0] = 0011) . . . . . . . . . . . . . . . . . . . . . . . 11-10 11.3.2.5 HI-Z (B[3:0] = 0100) . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 11.3.2.6 ENABLE_ONCE(B[3:0] = 0110) . . . . . . . . . . . . . . . . 11-11 11.3.2.7 DEBUG_REQUEST(B[3:0] = 0111) . . . . . . . . . . . . . 11-11 11.3.2.8 BYPASS (B[3:0] = 1111) . . . . . . . . . . . . . . . . . . . . . 11-11 11.4 DSP56300 RESTRICTIONS . . . . . . . . . . . . . . . . . . . . . . . 11-12 11.5 DSP56309 BOUNDARY SCAN REGISTER . . . . . . . . . . . 11-13 MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D xv Freescale Semiconductor, Inc. APPENDIX A BOOTSTRAP PROGRAMS . . . . . . . . . . . . . . . . . . A-1 Freescale Semiconductor, Inc... APPENDIX B EQUATES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 B.1 I/O EQUATES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3 B.2 HOST INTERFACE (HI08) EQUATES . . . . . . . . . . . . . . . . . B-3 B.3 SCI EQUATES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4 B.4 ESSI EQUATES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5 B.5 EXCEPTION PROCESSING EQUATES . . . . . . . . . . . . . . . B-7 B.6 TIMER MODULE EQUATES . . . . . . . . . . . . . . . . . . . . . . . . B-9 B.7 DIRECT MEMORY ACCESS (DMA) EQUATES . . . . . . . . B-10 B.8 PHASE-LOCKED LOOP (PLL) EQUATES . . . . . . . . . . . . . B-12 B.9 BUS INTERFACE UNIT (BIU) EQUATES . . . . . . . . . . . . . B-13 B.10 INTERRUPT EQUATES . . . . . . . . . . . . . . . . . . . . . . . . . . . B-15 APPENDIX C DSP56309 BSDL LISTING . . . . . . . . . . . . . . . . . . . C-1 APPENDIX D PROGRAMMING REFERENCE . . . . . . . . . . . . . . . D-1 D.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3 D.1.1 Peripheral Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3 D.1.2 Interrupt Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3 D.1.3 Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3 D.1.4 Programming Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3 D.2 INTERNAL I/O MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . D-4 D.3 INTERRUPT ADDRESSES AND SOURCES . . . . . . . . . . . D-11 D.4 INTERRUPT PRIORITIES. . . . . . . . . . . . . . . . . . . . . . . . . . D-13 xvi For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. LIST OF FIGURES Figure 1-1 Figure 2-1 Figure 3-1 DSP56309 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 Signals Identified by Functional Group . . . . . . . . . . . . . . . . . . . . 2-4 Default Settings (0, 0, 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Instruction Cache Enabled (0, 0, 1) . . . . . . . . . . . . . . . . . . . . . . 3-11 Switched Program RAM (0, 1, 0). . . . . . . . . . . . . . . . . . . . . . . . 3-12 Switched Program RAM and Instruction Cache Enabled (0, 1, 1)3-13 16-bit Space with Default RAM (1, 0, 0) . . . . . . . . . . . . . . . . . . 3-14 16-bit Space with Instruction Cache Enabled (1, 0, 1) . . . . . . . 3-15 16-bit Space with Switched Program RAM (1, 1, 0) . . . . . . . . . 3-16 16-bit Space, Switched Program RAM, Instruction Cache . . . . 3-17 Interrupt Priority Register C (IPR-C) (X:$FFFFFF) . . . . . . . . . . 4-13 Interrupt Priority Register P (IPR-P) (X:$FFFFFE) . . . . . . . . . . 4-13 DSP56309 Operating Mode Register (OMR) . . . . . . . . . . . . . . 4-17 PLL Control (PCTL) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 Identification Register Configuration (Revision 0) . . . . . . . . . . . 4-19 Address Attribute Registers (AAR0AAR3). . . . . . . . . . . . . . . . 4-20 HI08 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 Host Control Register (HCR) (X:$FFFFC2). . . . . . . . . . . . . . . . . 6-9 Host Status Register (HSR) (X:$FFFFC3) . . . . . . . . . . . . . . . . 6-11 Freescale Semiconductor, Inc... Figure 3-2 Figure 3-3 Figure 3-4 Figure 3-5 Figure 3-6 Figure 3-7 Figure 3-8 Figure 4-1 Figure 4-2 Figure 4-3 Figure 4-4 Figure 4-5 Figure 4-6 Figure 6-1 Figure 6-2 Figure 6-3 MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D xvii Freescale Semiconductor, Inc. Figure 6-4 Figure 6-5 Figure 6-6 Figure 6-7 Figure 6-8 Figure 6-9 Host Base Address Register (HBAR) (X:$FFFFC5). . . . . . . . . . 6-12 Self Chip Select Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 Host Port Control Register (HPCR) (X:$FFFFC4) . . . . . . . . . . . 6-13 Single Strobe Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 Dual Strobe Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 Host Data Direction Register (HDDR) (X:$FFFFC8) . . . . . . . . . 6-17 Host Data Register (HDR) (X:$FFFFC9) . . . . . . . . . . . . . . . . . . 6-17 HSR-HCR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 Interface Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 Command Vector Register (CVR) . . . . . . . . . . . . . . . . . . . . . . . 6-25 Interface Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 Interrupt Vector Register (IVR). . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 HI08 Host Request Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33 ESSI Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 ESSI Control Register A (CRA) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 ESSI Control Register B (CRB) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 ESSI Status Register (SSISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 ESSI Transmit Slot Mask Register A (TSMA) . . . . . . . . . . . . . . 7-10 ESSI Transmit Slot Mask Register B (TSMB) . . . . . . . . . . . . . . 7-10 ESSI Receive Slot Mask Register A (RSMA). . . . . . . . . . . . . . . 7-10 ESSI Receive Slot Mask Register B (RSMB). . . . . . . . . . . . . . . 7-10 ESSI Clock Generator Functional Block Diagram . . . . . . . . . . . 7-12 Freescale Semiconductor, Inc... Figure 6-10 Figure 6-11 Figure 6-12 Figure 6-13 Figure 6-14 Figure 6-15 Figure 6-16 Figure 7-1 Figure 7-2 Figure 7-3 Figure 7-4 Figure 7-5 Figure 7-6 Figure 7-7 Figure 7-8 Figure 7-9 xviii For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Figure 7-10 Figure 7-11 Figure 7-12 Figure 7-13 Figure 7-14 Figure 7-15 ESSI Frame Sync Generator Functional Block Diagram. . . . . . 7-13 CRB FSL0 and FSL1 Bit Operation (FSR = 0) . . . . . . . . . . . . . 7-19 CRB SYN Bit Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20 CRB MOD Bit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21 Normal Mode, External Frame Sync (8 Bit, 1 Word in Frame) . 7-22 Network Mode, External Frame Sync (8 Bit, 2 Words in Frame) 7-23 ESSI Data Path Programming Model (SHFD = 0). . . . . . . . . . . 7-31 ESSI Data Path Programming Model (SHFD = 1). . . . . . . . . . . 7-32 Port Control Register (PCR) (PCRC X:$FFFFBF). . . . . . . . . . . 7-44 Port Direction Register (PRR)(PRRC X:$FFFFBE). . . . . . . . . . 7-44 Port Data Register (PDR) (PDRC X:$FFFFBD) . . . . . . . . . . . . 7-45 SCI Control Register (SCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 SCI Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 SCI Clock Control Register (SCCR) . . . . . . . . . . . . . . . . . . . . . . 8-5 SCI Data Word Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 16 x Serial Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 SCI Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 SCI Programming Model Data Registers . . . . . . . . . . . . . . . . . 8-19 Port E Control Register (PCRE) . . . . . . . . . . . . . . . . . . . . . . . . 8-27 Port E Direction Register (PRRE) . . . . . . . . . . . . . . . . . . . . . . . 8-28 Port E Data Register (PDRE) . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29 Triple Timer Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . 9-4 Freescale Semiconductor, Inc... Figure 7-16 Figure 7-17 Figure 7-18 Figure 7-19 Figure 7-20 Figure 8-1 Figure 8-2 Figure 8-3 Figure 8-4 Figure 8-5 Figure 8-6 Figure 8-7 Figure 8-8 Figure 8-9 Figure 8-10 Figure 9-1 MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D xix Freescale Semiconductor, Inc. Figure 9-2 Figure 9-3 Figure 9-4 Figure 9-5 Figure 9-6 Figure 10-1 Timer Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 Timer Module ProgrammerOs Model . . . . . . . . . . . . . . . . . . . . . . . 9-6 Timer Prescaler Load Register (TPLR) . . . . . . . . . . . . . . . . . . . . 9-7 Timer Prescaler Count Register (TPCR) . . . . . . . . . . . . . . . . . . . 9-8 Timer Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 OnCE Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 OnCE Module Multiprocessor Configuration . . . . . . . . . . . . . . . 10-4 OnCE Controller Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . 10-5 OnCE Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 OnCE Status and Control Register (OSCR). . . . . . . . . . . . . . . . 10-8 OnCE Memory Breakpoint Logic 0. . . . . . . . . . . . . . . . . . . . . . 10-10 OnCE Breakpoint Control Register (OBCR). . . . . . . . . . . . . . . 10-12 OnCE Trace Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . 10-15 OnCE Pipeline Information and GDB Registers . . . . . . . . . . . 10-19 OnCE Trace Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22 TAP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 TAP Controller State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 JTAG Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 JTAG ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-15 Operating Mode Register (OMR) . . . . . . . . . . . . . . . . . . . . . . . . D-16 Freescale Semiconductor, Inc... Figure 10-2 Figure 10-3 Figure 10-4 Figure 10-5 Figure 10-6 Figure 10-7 Figure 10-8 Figure 10-9 Figure 10-10 Figure 11-1 Figure 11-2 Figure 11-3 Figure 11-4 Figure 11-5 Figure D-1 Figure D-2 xx For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Figure D-3 Figure D-4 Figure D-5 Figure D-6 Figure D-7 Figure D-8 Interrupt Priority RegisterCore (IPRC). . . . . . . . . . . . . . . . . . D-17 Interrupt Priority Register Peripherals (IPRP). . . . . . . . . . . . D-18 Phase-Locked Loop Control Register (PCTL) . . . . . . . . . . . . . . D-19 Host Receive and Host Transmit Data Registers . . . . . . . . . . . D-20 Host Control and Host Status Registers . . . . . . . . . . . . . . . . . . D-21 Host Base Address and Host Port Control Registers . . . . . . . . D-22 Interrupt Control and Interrupt Status Registers . . . . . . . . . . . . D-23 Interrupt Vector and Command Vector Registers . . . . . . . . . . . D-24 Host Receive and Host Transmit Data Registers . . . . . . . . . . . D-25 ESSI Control Register A (CRA) . . . . . . . . . . . . . . . . . . . . . . . . . D-26 ESSI Control Register B (CRB) . . . . . . . . . . . . . . . . . . . . . . . . . D-27 ESSI Status Register (SSISR). . . . . . . . . . . . . . . . . . . . . . . . . . D-28 ESSR Transmit and Receive Slot Mask Registers (TSM, RSM) D-29 SCI Control Register (SCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . D-30 SCI Status and Clock Control Registers (SSR, SCCR). . . . . . . D-31 SCI Receive and Transmit Data Registers (SRX, TRX) . . . . . . D-32 Timer Prescaler Load/Count Register (TPLR, TPCR). . . . . . . . D-33 Timer Control/Status Register (TCSR) . . . . . . . . . . . . . . . . . . . D-34 Timer Load, Compare, Count Registers (TLR, TCPR, TCR) . . D-35 Host Data Direction and Host Data Registers (HDDR, HDR) . . D-36 Port C Registers (PCRC, PRRC, PDRC) . . . . . . . . . . . . . . . . . D-37 Port D Registers (PCRD, PRRD, PDRD) . . . . . . . . . . . . . . . . . D-38 Freescale Semiconductor, Inc... Figure D-9 Figure D-10 Figure D-11 Figure D-12 Figure D-13 Figure D-14 Figure D-15 Figure D-16 Figure D-17 Figure D-18 Figure D-19 Figure D-20 Figure D-21 Figure D-22 Figure D-23 Figure D-24 MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D xxi Freescale Semiconductor, Inc. Figure D-25 Port E Registers (PCRE, PRRE, PDRE) . . . . . . . . . . . . . . . . . D-39 Freescale Semiconductor, Inc... xxii For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. LIST OF TABLES Table 1-1 Table 1-2 Table 2-1 High True/Low True Signal Conventions . . . . . . . . . . . . . . . . . . 1-5 On Chip Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 DSP56309 Functional Signal Groupings . . . . . . . . . . . . . . . . . . 2-3 Power Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Grounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Phase-Locked Loop Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 External Address Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 External Data Bus Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 External Bus Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Interrupt and Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 Host Port Usage Considerations . . . . . . . . . . . . . . . . . . . . . . . 2-17 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 Enhanced Synchronous Serial Interface 0 (ESSI0) . . . . . . . . . 2-24 Enhanced Synchronous Serial Interface 1 (ESSI1) . . . . . . . . . 2-28 Serial Communication Interface (SCI) . . . . . . . . . . . . . . . . . . . 2-32 Triple Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34 OnCE/JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35 Memory Space Configuration Bit Settings for the DSP56309 . . . 3-5 Freescale Semiconductor, Inc... Table 2-2 Table 2-3 Table 2-4 Table 2-5 Table 2-6 Table 2-7 Table 2-8 Table 2-9 Table 2-10 Table 2-11 Table 2-12 Table 2-13 Table 2-14 Table 2-15 Table 2-16 Table 3-1 MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D xxiii Freescale Semiconductor, Inc. Table 3-2 Table 3-3 Table 3-4 Table 3-5 Table 3-6 Table 4-1 RAM Configuration Bit Settings for the DSP56309 . . . . . . . . . . . 3-5 Memory Space Configurations for the DSP56309 . . . . . . . . . . . . 3-7 RAM Configurations for the DSP56309 . . . . . . . . . . . . . . . . . . . . 3-8 Memory Locations for Program RAM and Instruction Cache . . . . 3-8 Memory Locations for Data RAM . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 DSP56309 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 Interrupt Priority Level Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 Interrupt Source Priorities within an IPL . . . . . . . . . . . . . . . . . . 4-14 DMA Request Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 HI08 Signal Definitions for Various Operational Modes . . . . . . . . 6-6 HI08 Data Strobe Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 HI08 Host Request Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 Host Command Interrupt Priority List . . . . . . . . . . . . . . . . . . . . . 6-10 HDR and HDDR Functionality . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 DSP Side Registers after Reset . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 Host Side Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 TREQ and RREQ modes (HDRQ = 0) . . . . . . . . . . . . . . . . . . . . 6-23 TREQ and RREQ modes (HDRQ = 1) . . . . . . . . . . . . . . . . . . . . 6-23 INIT Command Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25 HREQ and HDRQ Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 Host Side Registers After Reset. . . . . . . . . . . . . . . . . . . . . . . . . 6-30 Freescale Semiconductor, Inc... Table 4-2 Table 4-3 Table 4-4 Table 4-5 Table 6-1 Table 6-2 Table 6-3 Table 6-4 Table 6-5 Table 6-6 Table 6-7 Table 6-8 Table 6-9 Table 6-10 Table 6-11 Table 6-12 xxiv For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Table 6-13 Table 7-1 Table 7-2 Table 7-3 Table 7-4 Table 7-5 HI08 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34 ESSI Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 ESSI Word Length Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 FSL1 and FSL0 Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 Mode and Signal Definition Table . . . . . . . . . . . . . . . . . . . . . . 7-24 Port Control Register and Port Direction Register Bits . . . . . . . 7-45 Word Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 TCM and RCM Bit Configuration . . . . . . . . . . . . . . . . . . . . . . . 8-17 SCI Registers after Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23 Port Control Register and Port Direction Register Bits . . . . . . . 8-28 Prescaler Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 Timer Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 Inverter (INV) Bit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 EX Bit Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 GO Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 R/W Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 OnCE Register Select Encoding . . . . . . . . . . . . . . . . . . . . . . . 10-6 Core Status Bits Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 Memory Breakpoint 0 and 1 Select Table . . . . . . . . . . . . . . . . 10-12 Breakpoint 0 Read/Write Select Table . . . . . . . . . . . . . . . . . . 10-13 Breakpoint 0 Condition Select Table . . . . . . . . . . . . . . . . . . . 10-13 Breakpoint 1 Read/Write Select Table . . . . . . . . . . . . . . . . . . 10-13 Freescale Semiconductor, Inc... Table 8-1 Table 8-2 Table 8-3 Table 8-4 Table 9-1 Table 9-2 Table 9-3 Table 10-1 Table 10-2 Table 10-3 Table 10-4 Table 10-5 Table 10-6 Table 10-7 Table 10-8 Table 10-9 MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D xxv Freescale Semiconductor, Inc. Table 10-10 Table 10-11 Table 10-12 Table 10-13 Table 10-14 Table 11-1 Breakpoint 1 Condition Select Table . . . . . . . . . . . . . . . . . . . . 10-14 Breakpoint 0 and 1 Event Select Table . . . . . . . . . . . . . . . . . . 10-14 TMS Sequencing for DEBUG_REQUEST . . . . . . . . . . . . . . . 10-29 TMS Sequencing for ENABLE_ONCE . . . . . . . . . . . . . . . . . . 10-30 TMS Sequencing for Reading Pipeline Registers . . . . . . . . . 10-31 JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 DSP56309 BSR Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . 11-13 Internal I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-4 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-11 Interrupt Source Priorities within an IPL . . . . . . . . . . . . . . . . . . D-13 Freescale Semiconductor, Inc... Table 11-2 Table D-1 Table D-2 Table D-3 xxvi For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. SECTION 1 DSP56309 OVERVIEW Freescale Semiconductor, Inc... MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 1-1 Freescale Semiconductor, Inc. DSP56309 Overview Freescale Semiconductor, Inc... 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 MANUAL ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 MANUAL CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 DSP56309 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 DSP56309 CORE DESCRIPTION . . . . . . . . . . . . . . . . . . . . 1-7 DSP56300 CORE FUNCTIONAL BLOCKS . . . . . . . . . . . . . 1-8 INTERNAL BUSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 DSP56309 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . 1-14 DIRECT MEMORY ACCESS (DMA) . . . . . . . . . . . . . . . . . . 1-15 DSP56309 ARCHITECTURE OVERVIEW . . . . . . . . . . . . . 1-15 1-2 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. DSP56309 Overview Introduction 1.1 INTRODUCTION This manual describes the DSP56309 24-bit digital signal processor (DSP), its memory, operating modes, and peripheral modules. The DSP56309 is an implementation of the DSP56300 core with a unique configuration of on-chip memory, cache, and peripherals. This manual is intended to be used with the DSP56300 Family Manual (DSP56300FM/AD), which describes the central processing unit (CPU), core programming models, and instruction set details. DSP56309 Technical Data (DSP56309/D) provides electrical specifications, timing, pinout, and packaging descriptions of the DSP56309. Freescale Semiconductor, Inc... You can obtain these documents, as well as MotorolaOs DSP development tools, through a local Motorola Semiconductor Sales Office or authorized distributor. To receive the latest information about this DSP, access the Motorola DSP home page at the address on the back cover of this document. 1.2 MANUAL ORGANIZATION This manual contains the following sections and appendices: Section 1NDSP56309 Overview Features list and block diagram Related documentation needed to use this chip The organization of this manual Signals on the DSP56309 pins and their functional groupings DSP56309 memory spaces, RAM configuration, memory configuration bit settings, memory configurations, and memory maps Registers for configuring the DSP56300 core to program the DSP56309, in particular the interrupt vector locations and the operation of the interrupt priority registers Operating modes and how they affect the processorOs program and data memories Section 2NSignal/Connection Descriptions Section 3NMemory Configuration Section 4NCore Configuration MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 1-3 Freescale Semiconductor, Inc. DSP56309 Overview Manual Organization Section 5NGeneral-Purpose I/O DSP56309 general-purpose input/output (GPIO) capability and the programming model for the GPIO signals (operation, registers, and control) 8-bit host interface (HI08), including a quick reference to the HI08 programming model 24-bit ESSI, which provides two identical full duplex UART-style serial ports for communications with devices such as codecs, DSPs, microprocessors, and peripherals implementing the Motorola serial peripheral interface (SPI) 24-bit SCI, a full duplex serial port for serial communication to DSPs, microcontrollers, or other peripherals (such as modems or other RS-232 devices) The three identical internal timers/event counter devices The On-Chip Emulation (OnCE) module, which is accessed through the JTAG port Specifics of the Joint Test Action Group (JTAG) port on the DSP56309 Bootstrap code used for the DSP56309 Equates (I/O, HI08, SCI, ESSI, exception processing, timer, DMA, PLL, BIU, and interrupts) for the DSP56309 BSDL listing for the DSP56309 Peripheral addresses, interrupt addresses, and interrupt priorities for the DSP56309 Programming sheets listing the contents of the major DSP56309 registers for programmerOs reference Section 6NHost Interface (HI08) Section 7NEnhanced Synchronous Serial Interface (ESSI) Freescale Semiconductor, Inc... Section 8NSerial Communication Interface (SCI) Section 9NTriple Timer Module Section 10NOn-Chip Emulation Module Section 11NJTAG Port Appendix ANBootstrap Programs Appendix BNEquates Appendix CNDSP56309 BSDL Listing Appendix DNProgramming Reference 1-4 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. DSP56309 Overview Manual Conventions 1.3 MANUAL CONVENTIONS This manual uses the following conventions: Bits within registers are always listed from most significant bit (MSB) to least significant bit (LSB). Bits within a register are indicated AA[n:m], n>m, when more than one bit is involved in a description. For purposes of description, the bits are presented as if they are contiguous within a register. However, this is not always the case. Refer to the programming model diagrams or to the programmerOs sheets to see the exact location of bits within a register. When a bit is described as Oset,O its value is 1. When a bit is described as Ocleared,O its value is 0. The word OassertO means that a high true (active high) signal is pulled high to VCC or that a low true (active low) signal is pulled low to ground. The word OdeassertO means that a high true signal is pulled low to ground or that a low true signal is pulled high to VCC. See Table 1-1. Table 1-1 High True/Low True Signal Conventions Signal/Symbol PIN1 PIN PIN PIN 1. 2. Freescale Semiconductor, Inc... Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage Ground2 VCC3 VCC Ground 3. PIN is a generic term for any pin on the chip. Ground is an acceptable low voltage level. See the appropriate data sheet for the range of acceptable low voltage levels (typically a TTL logic low). VCC is an acceptable high voltage level. See the appropriate data sheet for the range of acceptable high voltage levels (typically a TTL logic high). Pins or signals that are asserted low (made active when pulled to ground) In text, have an overbar. For example, RESET is asserted low. In code examples, have a tilde in front of their names. In Example 1-1, line 3 refers to the SS0 signal (shown as ~SS0). MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 1-5 Freescale Semiconductor, Inc. DSP56309 Overview DSP56309 Features Sets of signals are indicated by the first and last signals in the set, for instance HA1HA8. Code examples are displayed in a monospaced font, as shown in Example 1-1. Example 1-1 Sample Code Listing BFSET #$0007,X:PCC; Configure: ; MISO0, MOSI0, SCK0 for SPI master ; ~SS0 as PC3 for GPIO line 1 line 2 line 3 Freescale Semiconductor, Inc... Hex values are indicated with a dollar sign ($) preceding the hex value. For example, $FFFFFF is the X memory address for the core interrupt priority register (IPR-C). The word OresetO is used in four different contexts in this manual: the reset signal, written as RESET; the reset instruction, written as RESET; the reset operating state, written as Reset; and the reset function, written as reset. 1.4 DSP56309 FEATURES The DSP56309 is a member of the DSP56300 family of programmable CMOS DSPs. The DSP56309 uses the DSP56300 core, a high-performance engine with a single clock cycle per instruction. The DSP56300 core provides up to twice the performance of Motorola's popular DSP56000 core family, while retaining code compatibility. The DSP56300 core family offers a new level of performance in speed and power provided by its rich instruction set and low-power dissipation, enabling a new generation of wireless, telecommunications, and multimedia products. The DSP56300 core is composed of the data arithmetic logic unit (Data ALU), address generation unit (AGU), program controller (PC), instruction cache controller, bus interface unit, direct memory access (DMA) controller, On-Chip Emulation (OnCE) module, and a PLL-based clock oscillator. Significant architectural enhancements to the DSP56300 core family include a barrel shifter, 24-bit addressing, an instruction cache, and DMA. The DSP56300 core family members contain the DSP56300 core and additional modules. The modules are chosen from a library of standard pre-designed elements, such as memories and peripherals. New modules can be added to the library to meet customer 1-6 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. DSP56309 Overview DSP56309 Core Description specifications. A standard interface between the DSP56300 core and the on-chip memory and peripherals supports a wide variety of memory and peripheral configurations. The DSP56309 targets telecommunications applications, such as multi-line voice/data/fax processing, video conferencing, audio applications, control, and general digital signal processing. 1.5 DSP56309 CORE DESCRIPTION Freescale Semiconductor, Inc... The DSP56300 Family Manual fully describes core features; this manual describes pinout, memory, and peripheral features. 1.5.1 General Features 80/100 million instructions per second (MIPS) with a 80/100 MHz clock at 3.0 3.6 V Object-code compatible with the DSP56000 core Highly parallel instruction set 1.5.2 Hardware Debugging Support On-Chip Emulation (OnCEO) module Joint Test Action Group (JTAG) test access port (TAP) Address trace mode reflects internal program RAM accesses at the external port 1.5.3 Reduced Power Dissipation Very low-power CMOS design Wait and stop low-power standby modes Fully-static logic, operation frequency down to 0 Hz (dc) Optimized cycle-by-cycle power management circuitry (instruction-dependent, peripheral-dependent, and mode-dependent) MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 1-7 Freescale Semiconductor, Inc. DSP56309 Overview DSP56300 Core Functional Blocks 1.6 DSP56300 CORE FUNCTIONAL BLOCKS The DSP56300 core provides the following functional blocks: Data ALU AGU PCU PLL and Clock Oscillator JTAG TAP and OnCE module Memory In addition, the DSP56309 provides a set of on-chip peripherals, described in Section 1.10. Freescale Semiconductor, Inc... 1.6.1 Data ALU The Data ALU performs all the arithmetic and logical operations on data operands in the DSP56300 core. The components of the Data ALU are as follows: Fully pipelined 24 24-bit parallel multiplier-accumulator (MAC) Bit field unit, comprising a 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing) Conditional ALU instructions 24-bit or 16-bit arithmetic support under software control Four 24-bit input general-purpose registers: X1, X0, Y1, and Y0 Six Data ALU registers (A2, A1, A0, B2, B1, and B0) that are concatenated into two general-purpose, 56-bit accumulators, A and B, accumulator shifters Two data bus shifter/limiter circuits 1.6.1.1 Data ALU Registers The Data ALU registers can be read or written over the X data bus (XDB) and the Y data bus (YDB) as 16- or 32-bit operands. The source operands for the Data ALU, which can be 16, 32, or 40 bits, always originate from Data ALU registers. The results of all Data ALU operations are stored in an accumulator. 1-8 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. DSP56309 Overview DSP56300 Core Functional Blocks All the Data ALU operations are performed in two clock cycles in pipeline fashion so that a new instruction can be initiated in every clock, yielding an effective execution rate of one instruction per clock cycle. The destination of every arithmetic operation can be used as a source operand for the immediately following operation without penalty. 1.6.1.2 Multiplier-Accumulator (MAC) The MAC unit comprises the main arithmetic processing unit of the DSP56300 core and performs all of the calculations on data operands. For arithmetic instructions, the unit accepts as many as three input operands and outputs one 56-bit result of the following form, Extension:Most Significant Product:Least Significant Product (EXT:MSP:LSP). Freescale Semiconductor, Inc... The multiplier executes 24-bit 24-bit, parallel, fractional multiplies between twos-complement signed, unsigned, or mixed operands. The 48-bit product is right-justified and added to the 56-bit contents of either the A or B accumulator. A 56-bit result can be stored as a 24-bit operand. The LSP can either be truncated or rounded into the MSP. Rounding is performed if specified. 1.6.2 Address Generation Unit (AGU) The AGU performs the effective address calculations using integer arithmetic necessary to address data operands in memory and contains the registers that generate the addresses. It implements four types of arithmetic: linear, modulo, multiple wrap-around modulo, and reverse-carry. The AGU operates in parallel with other chip resources to minimize address-generation overhead. The AGU is divided into two halves, each with its own address arithmetic logic unit (Address ALU). Each Address ALU has four sets of register triplets, and each register triplet is composed of an address register, an offset register, and a modifier register. The two Address ALUs are identical. Each contains a 16-bit full adder (called an offset adder). A second full adder (called a modulo adder) adds the summed result of the first full adder to a modulo value that is stored in its respective modifier register. A third full adder (called a reverse-carry adder) is also provided. The offset adder and the reverse-carry adder are in parallel and share common inputs. The only difference between them is that they carry propagates in opposite directions. Test logic determines which of the three summed results of the full adders is output. Each Address ALU can update one address register from its respective address register file during one instruction cycle. The contents of the associated modifier register MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 1-9 Freescale Semiconductor, Inc. DSP56309 Overview DSP56300 Core Functional Blocks specifies the type of arithmetic to be used in the address register update calculation. The modifier value is decoded in the Address ALU. 1.6.3 Program Control Unit (PCU) The PCU performs instruction prefetch, instruction decoding, hardware DO loop control, and exception processing. The PCU implements a seven-stage pipeline and controls the different processing states of the DSP56300 core. The PCU consists of three hardware blocks: Freescale Semiconductor, Inc... Program decode controller (PDC) Program address generator (PAG) Program interrupt controller The PDC decodes the 24-bit instruction loaded into the instruction latch and generates all signals necessary for pipeline control. The PAG contains all the hardware needed for program address generation, system stack, and loop control. The PIC arbitrates among all interrupt requests (internal interrupts, as well as the five external requests IRQA, IRQB, IRQC, IRQD, and NMI) and generates the appropriate interrupt vector address. PCU features include the following: Position Independent Code (PIC) support Addressing modes optimized for DSP applications (including immediate offsets) On-chip instruction cache controller On-chip memory-expandable hardware stack Nested hardware DO loops Fast auto-return interrupts The PCU implements its functions using the following registers: PCNprogram counter register SRNstatus register LANloop address register LCNloop counter register VBANvector base address register SZNsize register 1-10 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. DSP56309 Overview DSP56300 Core Functional Blocks SPNstack pointer OMRNoperating mode register SCNstack counter register The PCU also includes a hardware system stack (SS). 1.6.4 PLL and Clock Oscillator Freescale Semiconductor, Inc... The clock generator in the DSP56300 core is composed of two main blocks: the PLL, which performs clock input division, frequency multiplication, and skew elimination; and the clock generator (CLKGEN), which performs low-power division and clock pulse generation. Allows change of low-power divide factor (DF) without loss of lock Output clock with skew elimination The PLL allows the processor to operate at a high internal clock frequency using a low-frequency clock input, a feature that offers two immediate benefits: A lower-frequency clock input reduces the overall electromagnetic interference generated by a system. The ability to oscillate at different frequencies reduces costs by eliminating the need to add additional oscillators to a system. 1.6.5 JTAG TAP and OnCE Module The DSP56300 core provides a dedicated user-accessible Test Access Port (TAP) that is fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Problems associated with testing high density circuit boards have led to development of this standard under the sponsorship of the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG). The DSP56300 core implementation supports circuit-board test strategies based on this standard. The test logic includes a TAP consisting of four dedicated signals, a 16-state controller, and three test data registers. A boundary scan register links all device signals into a single shift register. The test logic, implemented utilizing static logic design, is independent of the device system logic. More information on the JTAG port is provided in Section 11NJTAG Port. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 1-11 Freescale Semiconductor, Inc. DSP56309 Overview DSP56300 Core Functional Blocks The OnCE module provides a means of interacting with the DSP56300 core and its peripherals non-intrusively so that a user can examine registers, memory, or on-chip peripherals. This facilitates hardware and software development on the DSP56300 core processor. OnCE module functions are provided through the JTAG TAP signals. More information about the OnCE module is provided in Section 10NOn-Chip Emulation Module. 1.6.6 On-Chip Memory Freescale Semiconductor, Inc... The memory space of the DSP56300 core is partitioned into program memory space, X data memory space, and Y data memory space. The data memory space is divided into X data memory and Y data memory in order to work with the two Address ALUs and to feed two operands simultaneously to the Data ALU. Memory space includes internal RAM and ROM and can be expanded off-chip under software control. More information about the internal memory is provided in Section 3NMemory Configuration. Program RAM, instruction cache, X data RAM, and Y data RAM size are programmable, as indicated in Table 1-2. Table 1-2 On Chip Memory Instruction Cache disabled enabled disabled enabled Switch Mode disabled disabled enabled enabled Program RAM Size 20K 24-bit 19K 24-bit 24K 24-bit 23K 24-bit Instruction Cache Size 0 1K 24-bit 0 1K 24-bit X Data RAM Size 7K 24-bit 7K 24-bit 5K 24-bit 5K 24-bit Y Data RAM Size 7K 24-bit 7K 24-bit 5K 24-bit 5K 24-bit There is an on-chip 192 x 24-bit bootstrap ROM. 1.6.7 Off-Chip Memory Expansion Memory can be expanded off-chip to do the following: Data memory expansion to two 256K 24-bit word memory spaces (or up to two4 M 24-bit word memory spaces by using the address attribute AA0AA3 signals) Program memory expansion to one 256K 24-bit words memory space (or up to one 4 M 24-bit word memory space by using the address attribute AA0AA3 signals) Additional features of off-chip memory include the following: 1-12 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. DSP56309 Overview Internal Buses External memory expansion port Simultaneous glueless interface to static random access memory (SRAM) and dynamic random access memory (DRAM) Supports interleaved, non-interfering access to both types of memory without losing in-page DRAM access, including DMA-driven access 1.7 INTERNAL BUSES Freescale Semiconductor, Inc... The following buses provide data exchange between the functional blocks of the core: Peripheral I/O expansion bus (PIO_EB) to peripherals Program memory expansion bus (PM_EB) to Program RAM X memory expansion bus (XM_EB) to X memory Y memory expansion bus (YM_EB) to Y memory Global data bus (GDB) between PCU and other core structures Program data bus (PDB) for carrying program data throughout the core X memory data bus (XDB) for carrying X data throughout the core Y memory data bus (YDB) for carrying Y data throughout the core Program address bus (PAB) for carrying program memory addresses throughout the core X memory address bus (XAB) for carrying X memory addresses throughout the core Y memory address bus (YAB) for carrying Y memory addresses throughout the core All internal buses on the DSP56300 family members are 16-bit buses except the PDB, which is a 24-bit bus. Figure 1-1 shows a block diagram of the DSP56309. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 1-13 Freescale Semiconductor, Inc. DSP56309 Overview DSP56309 Block Diagram 1.8 DSP56309 BLOCK DIAGRAM 16 6 6 3 Memory Expansion Area Triple Timer Host Interface HI08 ESSI Interface SCI Interface Program RAM X Data RAM Y Data RAM PIO_EB PM_EB Freescale Semiconductor, Inc... Address Generation Unit Six Channel DMA Unit Bootstrap ROM YAB XAB PAB DAB YM_EB Peripheral Expansion Area XM_EB External Address Bus Switch 18 ADDRESS 24-Bit DSP56300 Core DDB YDB External Bus 13 Interface & I - Cache CONTROL Control Internal Data Bus Switch EXTAL XTAL Clock Generator PLL 2 RESET PINIT/NMI Program Interrupt Controller Program Decode Controller MODD/IRQA MODC/IRQB MODB/IRQC MODA/IRQD XDB PDB GDB External Data Bus Switch 24 DATA Program Address Generator Data ALU 24 24 + 56 (R) 56-bit MAC Two 56-bit Accumulators 56-bit Barrel Shifter Power Mgmt JTAG OnCE 6 AA0456 Figure 1-1 DSP56309 Block Diagram Note: See Section 1.6.6 On-Chip Memory on page 1-12 for details on memory size. 1-14 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. DSP56309 Overview Direct Memory Access (DMA) 1.9 DIRECT MEMORY ACCESS (DMA) The DMA block has the following features: Six DMA channels supporting internal and external accesses One-, two-, and three-dimensional transfers (including circular buffering) End-of-block-transfer interrupts Triggering from interrupt lines, all peripherals, and DMA channels Freescale Semiconductor, Inc... 1.10 DSP56309 ARCHITECTURE OVERVIEW The DSP56309 performs a wide variety of fixed-point digital signal processing functions. In addition to the core features previously discussed, the DSP56309 provides the following peripherals: Enhanced DSP56000-like 8-bit parallel host interface (HI08) supports a variety of buses (e.g., industry standard architecture) and provides glueless connection to a number of industry standard microcomputers, microprocessors, and DSPs Two enhanced synchronous serial interfaces (ESSI0 and ESSI1), each with one receiver and three transmitters (allows six-channel home theater) Serial communications interface (SCI) with baud rate generator Triple timer module Up to 34 programmable general purpose input/output (GPIO) pins, depending on which peripherals are enabled 1.10.1 GPIO Functionality The GPIO port consists of as many as thirty-four programmable signals, all of which are also used by the peripherals (HI08, ESSI, SCI, and timer). There are no dedicated GPIO signals. Peripheral pins are configured as GPIO inputs after any reset. (Data in the port data register is not affected by a reset.) The GPIO functionality for each peripheral is controlled by three memory-mapped registers per peripheral. The techniques for register programming for all GPIO functionality is very similar between these interfaces. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 1-15 Freescale Semiconductor, Inc. DSP56309 Overview DSP56309 Architecture Overview 1.10.2 Host Interface (HI08) The HI08 is a byte-wide, full-duplex, double-buffered, parallel port that can connect directly to the data bus of a host processor. The HI08 supports a variety of buses and connects to a number of industry-standard DSPs, microcomputers, and microprocessors without requiring additional logic. The DSP core treats the HI08 as a memory-mapped peripheral occupying eight 24-bit words in data memory space. The DSP can use the HI08 as a memory-mapped peripheral, using either standard polled or interrupt programming techniques. Separate transmit and receive data registers are double-buffered to allow the DSP and host processor to transfer data efficiently at high speed. Memory mapping allows DSP core communication with the HI08 registers using standard instructions and addressing modes. Freescale Semiconductor, Inc... 1.10.3 Enhanced Synchronous Serial Interface (ESSI) On the DSP56309 are two independent and identical ESSIs. Each ESSI has a full-duplex serial port for communication with a variety of serial devices, including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals that implement the Motorola SPI. The ESSI consists of independent transmitter and receiver sections and a common ESSI clock generator. The capabilities of the ESSI include the following: Independent (asynchronous) or shared (synchronous) transmit and receive sections with separate or shared internal/external clocks and frame syncs Normal mode operation using frame sync Network mode operation with as many as 32 time slots Programmable word length (8, 12, or 16 bits) Program options for frame synchronization and clock generation One receiver and three transmitters per ESSI allows six-channel home theater 1.10.4 Serial Communications Interface (SCI) The DSP56309Os SCI provides a full-duplex port for serial communication with other DSPs, microprocessors, or peripherals such as modems. The SCI interfaces without 1-16 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. DSP56309 Overview DSP56309 Architecture Overview additional logic to peripherals that use TTL-level signals. With a small amount of additional logic, the SCI can connect to peripheral interfaces that have non-TTL level signals, such as the RS-232C, RS-422, etc. This interface uses three dedicated signals: transmit data (TXD), receive data (RXD), and SCI serial clock (SCLK). It supports industry-standard asynchronous bit rates and protocols, as well as high-speed synchronous data transmission (up to 8.25 Mbps for a 66 MHz clock). The asynchronous protocols supported by the SCI include a multidrop mode for master/slave operation with wakeup on idle line and wakeup on address bit capability. This mode allows the DSP56309 to share a single serial line efficiently with other peripherals. Freescale Semiconductor, Inc... The SCI consists of separate transmit and receive sections that can operate asynchronously with respect to each other. A programmable baud-rate generator provides the transmit and receive clocks. An enable vector and an interrupt vector have been included so that the baud-rate generator can function as a general purpose timer when it is not being used by the SCI or when the interrupt timing is the same as that used by the SCI. 1.10.5 Timer Module The triple timer module is composed of a common 21-bit prescaler and three independent and identical general-purpose 24-bit timer/event counters, each with its own memory-mapped register set. Each timer has a single signal that can function as a GPIO signal or as a timer signal. Each timer can use internal or external clocking and can interrupt the DSP after a specified number of events (clocks) or can signal an external device after counting internal events. Each timer connects to the external world through one bidirectional signal. When this signal is configured as an input, the timer can function as an external event counter or measures external pulse width/signal period. When the signal is used as an output, the timer can function as either a timer, a watchdog, or a Pulse Width Modulator (PWM). MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 1-17 Freescale Semiconductor, Inc. DSP56309 Overview DSP56309 Architecture Overview Freescale Semiconductor, Inc... 1-18 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. SECTION 2 SIGNAL/CONNECTION DESCRIPTIONS Freescale Semiconductor, Inc... MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 2-1 Freescale Semiconductor, Inc. Signal/Connection Descriptions Freescale Semiconductor, Inc... 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 SIGNAL GROUPINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 POWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 GROUND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 PHASE-LOCKED LOOP (PLL) . . . . . . . . . . . . . . . . . . . . . . . 2-8 EXTERNAL MEMORY EXPANSION PORT (PORT A). . . . . 2-9 INTERRUPT AND MODE CONTROL . . . . . . . . . . . . . . . . . 2-14 HOST INTERFACE (HI08) . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 ENHANCED SYNCHRONOUS SERIAL INTERFACE . . . . 2-24 SERIAL COMMUNICATION INTERFACE (SCI) . . . . . . . . . 2-32 TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33 ONCE/JTAG INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . 2-35 2-2 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Signal/Connection Descriptions Signal Groupings 2.1 SIGNAL GROUPINGS The DSP56309 input and output signals are organized into functional groups, as shown in Table 2-1 and as illustrated in Figure 2-1. The DSP56309 is operated from a 3 V supply. Table 2-1 DSP56309 Functional Signal Groupings Functional Group Number of Signals 20 19 2 3 18 Port A1 24 13 5 Port B2 Ports C and D3 Port E4 16 12 Detailed Description Table 2-2 Table 2-3 Table 2-4 Table 2-5 Table 2-6 Table 2-7 Table 2-8 Table 2-9 Table 2-11 Table 2-12 and Table 2-13 Table 2-14 Table 2-15 Table 2-16 Freescale Semiconductor, Inc... Power (VCC) Ground (GND) Clock PLL Address Bus Data Bus Bus Control Interrupt and Mode Control Host Interface (HI08) Enhanced Synchronous Serial Interface (ESSI) Serial Communication Interface (SCI) Timer OnCE/JTAG Port Note: 1. 2. 3. 4. 3 3 6 Port A signals define the external memory interface port, including the external address bus, data bus, and control signals. Port B signals are the HI08 port signals multiplexed with the GPIO signals. Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals. Port E signals are the SCI port signals multiplexed with the GPIO signals. Figure 2-1 is a diagram of DSP56309 signals by functional group. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 2-3 Freescale Semiconductor, Inc. Signal/Connection Descriptions Signal Groupings fs DSP56309 PLL Core Logic I/O Address Bus Data Bus Bus Control HI08 ESSI/SCI/Timer PLL PLL Internal Logic Address Bus Data Bus Bus Control HI08 ESSI/SCI/Timer VCCP VCCQL VCCQH VCCA VCCD VCCC VCCH VCCS 4 3 3 4 2 2 Freescale Semiconductor, Inc... GNDP GNDP1 GNDQ GNDA GNDD GNDC GNDH GNDS EXTAL XTAL CLKOUT PCAP After Reset NMI 4 4 4 2 2 After Reset During Reset MODA IRQA MODB IRQB MODC IRQC IRQD MODD RESET RESET Host Interface (H108)1 Non-Multiplexed Multiplexed Port B Bus Bus GPIO 8 H0H7 HAD0HAD7 PB0PB7 HA0 HAS/HAS PB8 HA1 HA8 PB9 HA2 HA9 PB10 HCS/HCS HA10 PB13 Single DS Double DS HRW HRD/HRD PB11 HDS/HDS HWR/HWR PB12 Single HR Double HR HREQ/HREQ HTRQ/HTRQ PB14 HACK/HACK HRRQ/HRRQ PB15 Enhanced Synchronous Serial Interface (ESSI0) Port C GPIO 3 SC00SC02 PC0PC2 SCK0 PC3 SRD0 PC4 STD0 PC5 Enhanced Synchronous Serial Interface (ESSI1) Port D GPIO 3 PD0PD2 SC10SC12 PD3 SCK1 PD4 SRD1 PD5 STD1 Serial Communications Interface (SCI)2 Port E GPIO EXTERNAL MEMORY INTERFACE A0A17 D0D23 AA0AA3/ RAS0RAS3 RD WR TA BR BG BB CAS BCLK BCLK Notes: 1. 18 Port D During Reset PINIT Port C Port B Port E Power Inputs Grounds Clock PLL 4 24 RXD TXD SCLK Timers3 TIO0 TIO1 TIO2 TCK TDI TDO TMS TRST DE PE0 PE1 PE2 GPIO TIO0 TIO1 TIO2 2. 3. The HI08 port supports a non-multiplexed or a multiplexed bus, single or double Data Strobe (DS), and single or double Host Request (HR) configurations. Since each of these modes is configured independently, any combination of these modes is possible. These HI08 signals can also be configured alternately as GPIO signals (PB0PB15). Signals with dual designations (e.g., HAS/HAS) have configurable polarity. The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC0PC5), Port D GPIO signals (PD0PD5), and Port E GPIO signals (PE0PE2), respectively. AA0601 TIO0TIO2 can be configured as GPIO signals. Figure 2-1 Signals Identified by Functional Group 2-4 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D OnCE/JTAG Port A MOTOROLA Freescale Semiconductor, Inc. Signal/Connection Descriptions Power 2.2 POWER Power input descriptions for the DSP56309 are listed in Table 2-2. Table 2-2 Power Inputs Power Name VCCP Description PLL PowerNVCCP is power dedicated for phase-locked loop (PLL) use. The voltage should be well regulated, and the input should be provided with an extremely low impedance path to the VCC power rail. VCCP should be bypassed to GNDP by a stabilizing capacitor located as close as possible to the chip package. There is one VCCP input. Quiet Core (Low) PowerNVCCQL is an isolated power for the core processing logic. This input must be isolated externally from all other chip power inputs. The user must provide adequate external decoupling capacitors. There are four VCCQL inputs. Quiet External (High) PowerNVCCQH is a quiet power source for I/O lines. This input must be tied externally to all other chip power inputs, except VCCQL. The user must provide adequate external decoupling capacitors. There are three VCCQH inputs. Address Bus PowerNVCCA is an isolated power for sections of the address bus I/O drivers. This input must be tied externally to all other chip power inputs except VCCQL. The user must provide adequate external decoupling capacitors. There are three VCCA inputs. Data Bus PowerNVCCD is an isolated power for sections of the data bus I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are four VCCD inputs. Bus Control PowerNVCCC is an isolated power for the bus control I/O drivers. This input must be tied externally to all other chip power inputs except VCCQL. The user must provide adequate external decoupling capacitors. There are two VCCC inputs. Host PowerNVCCH is an isolated power for the HI08 I/O drivers. This input must be tied externally to all other chip power inputs except VCCQL. The user must provide adequate external decoupling capacitors. There is one VCCH input. Freescale Semiconductor, Inc... VCCQL (4) VCCQH (3) VCCA (3) VCCD (4) VCCC (2) VCCH MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 2-5 Freescale Semiconductor, Inc. Signal/Connection Descriptions Ground Table 2-2 Power Inputs (Continued) Power Name VCCS (2) Description ESSI, SCI, and Timer PowerNVCCS is an isolated power for the ESSI, SCI, and timer I/O drivers. This input must be tied externally to all other chip power inputs except VCCQL. The user must provide adequate external decoupling capacitors. There are two VCCS inputs. Note: Freescale Semiconductor, Inc... These designations are package-dependent. Some packages connect all VCC inputs except VCCP to each other internally. On those packages, all power input, except VCCP, are labeled VCC. The number of connections indicated in this table are minimum values; the total VCC connections are package-dependent. 2.3 GROUND Ground descriptions for the DSP56309 are listed in Table 2-3. Table 2-3 Grounds Ground Name GNDP Description PLL GroundNGNDP is a ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. VCCP should be bypassed to GNDP by a 0.47 mF capacitor located as close as possible to the chip package. There is one GNDP connection. PLL Ground 1NGNDP1 is a ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. There is one GNDP1 connection. Quiet GroundNGNDQ is an isolated ground for the internal processing logic. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GNDQ connections. Address Bus GroundNGNDA is an isolated ground for sections of the address bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GNDA connections. GNDP1 GNDQ (4) GNDA (4) 2-6 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Signal/Connection Descriptions Clock Table 2-3 Grounds (Continued) Ground Name GNDD (4) Description Data Bus GroundNGNDD is an isolated ground for sections of the data bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GNDD connections. Bus Control GroundNGNDC is an isolated ground for the bus control I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are two GNDC connections. Host GroundNGNDH is an isolated ground for the HI08 I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There is one GNDH connection. ESSI, SCI, and Timer GroundNGNDS is an isolated ground for the ESSI, SCI, and timer I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are two GNDS connections. GNDC (2) Freescale Semiconductor, Inc... GNDH GNDS (2) Note: These designations are package-dependent. Some packages connect all GND inputs, except GNDP and GNDP1, to each other internally. On those packages, all ground connections, except GNDP and GNDP1, are labeled GND. The number of connections indicated in this table are minimum values; the total GND connections are package-dependent. 2.4 CLOCK Clock Signal descriptions for the DSP56309 are listed in Table 2-4. Table 2-4 Clock Signals Signal Name EXTAL Type Input State During Reset Input Signal Description External Clock/Crystal InputNEXTAL interfaces the internal crystal oscillator input to an external crystal or an external clock. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 2-7 Freescale Semiconductor, Inc. Signal/Connection Descriptions Phase-Locked Loop (PLL) Table 2-4 Clock Signals (Continued) Signal Name XTAL Type Output State During Reset Chip-driven Signal Description Crystal OutputNXTAL connects the internal crystal oscillator output to an external crystal. If an external clock is used, leave XTAL unconnected. Freescale Semiconductor, Inc... 2.5 PHASE-LOCKED LOOP (PLL) Phase-locked loop signal descriptions are listed in Table 2-5. Table 2-5 Phase-Locked Loop Signals Signal Name PCAP Type Input State During Reset Input Signal Description PLL CapacitorNPCAP is an input connecting an off-chip capacitor to the PLL filter. Connect one capacitor terminal to PCAP and the other terminal to VCCP. If the PLL is not used, PCAP can be tied to VCC, tied to GND, or left floating. CLKOUT Output Chip-driven Clock OutputNCLKOUT provides an output clock synchronized to the internal core clock phase. If the PLL is enabled and both the multiplication and division factors equal one, then CLKOUT is also synchronized to EXTAL. If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL. 2-8 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Signal/Connection Descriptions External Memory Expansion Port (Port A) Table 2-5 Phase-Locked Loop Signals (Continued) Signal Name PINIT/ NMI Type Input State During Reset Input Signal Description PLL Initial/Non-Maskable InterruptNDuring assertion of RESET, the value of PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register, determining whether the PLL is enabled or disabled. After RESET deassertion and during normal instruction processing, the PINIT/NMI Schmitt-trigger input is a negative-edge-triggered Non-Maskable Interrupt (NMI) request internally synchronized to CLKOUT. Freescale Semiconductor, Inc... 2.6 EXTERNAL MEMORY EXPANSION PORT (PORT A) When the DSP56309 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-states the relevant Port A signals: A0A17, D0D23, AA0/RAS0AA3/RAS3, RD, WR, BB, CAS, BCLK, BCLK. 2.6.1 External Address Bus External address bus signals for the DSP56309 are listed in Table 2-6. Table 2-6 External Address Bus Signals Signal Name A0A17 Type Output State During Reset Tri-stated Signal Description Address BusNWhen the DSP is the bus master, A0A17 are active-high outputs that specify the address for external program and data memory accesses. Otherwise, the signals are tri-stated. To minimize power dissipation, A0A17 do not change state when external memory spaces are not being accessed. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 2-9 Freescale Semiconductor, Inc. Signal/Connection Descriptions External Memory Expansion Port (Port A) 2.6.2 External Data Bus External data bus signals for the DSP56309 are listed in Table 2-7. Table 2-7 External Data Bus Signals Signal Name D0D23 Type Input/ Output State During Reset weakly driven by bus keeper Signal Description Data BusNWhen the DSP is the bus master, D0D23 are active-high, bidirectional input/outputs that provide the bidirectional data bus for external program and data memory accesses. Otherwise, D0D23 are weakly driven by the bus keeper. Freescale Semiconductor, Inc... 2.6.3 External Bus Control External bus control signal descriptions for the DSP56309 are listed in Table 2-8. Table 2-8 External Bus Control Signals Signal Name AA0 AA3/ RAS0 RAS3 Type Output State During Reset Tri-stated Signal Description Address Attribute or Row Address StrobeNWhen defined as AA, these signals can be used as chip selects or additional address lines. When defined as RAS, these signals can be used as RAS for DRAM interface. These signals are tri-statable outputs with programmable polarity. Read EnableNWhen the DSP is the bus master, RD is an active-low output that is asserted to read external memory on the data bus (D0D23). Otherwise, RD is tri-stated. Write EnableNWhen the DSP is the bus master, WR is an active-low output that is asserted to write external memory on the data bus (D0D23). Otherwise, the signals are tri-stated. RD Output Tri-stated WR Output Tri-stated 2-10 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Signal/Connection Descriptions External Memory Expansion Port (Port A) Table 2-8 External Bus Control Signals (Continued) Signal Name TA Type Input State During Reset Ignored Input Signal Description Transfer AcknowledgeNIf the DSP56309 is the bus master and there is no external bus activity, or the DSP56309 is not the bus master, the TA input is ignored. The TA input is a data transfer acknowledge (DTACK) function that can extend an external bus cycle indefinitely. Any number of wait states (1, 2,..., infinity) can be added to the wait states inserted by the BCR by keeping TA deasserted. In typical operation, TA is deasserted at the start of a bus cycle, is asserted to enable completion of the bus cycle, and is deasserted before the next bus cycle. The current bus cycle completes one clock period after TA is asserted synchronous to CLKOUT. The number of wait states is determined by the TA input or by the BCR, whichever is longer. The BCR can be used to set the minimum number of wait states in external bus cycles. In order to use the TA functionality, the BCR must be programmed to at least one wait state. A zero wait state access cannot be extended by TA deassertion; otherwise, improper operation can result. TA can operate synchronously or asynchronously depending on the setting of the TAS bit in the OMR. You must not use TA functionality while performing DRAM type accesses; otherwise, improper operation can result. Freescale Semiconductor, Inc... MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 2-11 Freescale Semiconductor, Inc. Signal/Connection Descriptions External Memory Expansion Port (Port A) Table 2-8 External Bus Control Signals (Continued) Signal Name BR Type Output State During Reset Output (deasserted) Signal Description Bus RequestNBR is an active-low output, never tri-stated. BR is asserted when the DSP requests bus mastership. BR is deasserted when the DSP no longer needs the bus. BR can be asserted or deasserted independent of whether the DSP56309 is a bus master or a bus slave. Bus OparkingO allows BR to be deasserted even though the DSP56309 is the bus master; see the description of bus OparkingO in the BB signal description. The bus request hole (BRH) bit in the BCR allows BR to be asserted under software control even though the DSP does not need the bus. BR is typically sent to an external bus arbitrator that controls the priority, parking, and tenure of each master on the same external bus. BR is only affected by DSP requests for the external bus, never for the internal bus. During hardware reset, BR is deasserted and the arbitration is reset to the bus slave state. Bus GrantNBG is an active-low input. BG must be asserted/deasserted synchronous to CLKOUT for proper operation. BG is asserted by an external bus arbitration circuit when the DSP56309 becomes the next bus master. When BG is asserted, the DSP56309 must wait until BB is deasserted before taking bus mastership. When BG is deasserted, bus mastership is typically given up at the end of the current bus cycle. This can occur in the middle of an instruction that requires more than one external bus cycle for execution. Freescale Semiconductor, Inc... BG Input Ignored Input 2-12 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Signal/Connection Descriptions External Memory Expansion Port (Port A) Table 2-8 External Bus Control Signals (Continued) Signal Name BB Type Input/ Output State During Reset Input Signal Description Bus BusyNBB is a bidirectional active-low input/output and must be asserted and deasserted synchronous to CLKOUT. BB indicates that the bus is active. Only after BB is deasserted can the pending bus master become the bus master (and then assert the signal again). The bus master can keep BB asserted after ceasing bus activity regardless of whether BR is asserted or deasserted. This is called Obus parkingO and allows the current bus master to reuse the bus without rearbitration until another device requires the bus. The deassertion of BB is done by an Oactive pull-upO method (i.e., BB is driven high and then released and held high by an external pull-up resistor). BB requires an external pull-up resistor. CAS Output Tri-stated Column Address StrobeNWhen the DSP is the bus master, CAS is an active-low output used by DRAM to strobe the column address. Otherwise, if the Bus Mastership Enable (BME) bit in the DRAM Control Register is cleared, the signal is tri-stated. Bus ClockNWhen the DSP is the bus master, BCLK is an active-high output. BCLK is active as a sampling signal when the program address tracing mode is enabled (by setting the ATE bit in the OMR). When BCLK is active and synchronized to CLKOUT by the internal PLL, BCLK precedes CLKOUT by 1/4 of a clock cycle. The BCLK rising edge can be used to sample the internal program memory access on the A0A23 address lines. Bus Clock NotNWhen the DSP is the bus master, BCLK is an active-low output and is the inverse of the BCLK signal. Otherwise, the signal is tri-stated. Freescale Semiconductor, Inc... BCLK Output Tri-stated BCLK Output Tri-stated MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 2-13 Freescale Semiconductor, Inc. Signal/Connection Descriptions Interrupt and Mode Control 2.7 INTERRUPT AND MODE CONTROL The interrupt and mode control signals select the chipOs operating mode as it comes out of hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines. Table 2-9 Interrupt and Mode Control Signal Name Type Input State During Reset Input Signal Description ResetNRESET is an active-low, Schmitt-trigger input. Deassertion of RESET is internally synchronized to the clock out (CLKOUT). When asserted, the chip is placed in the Reset state and the internal phase generator is reset. The Schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. If RESET is deasserted synchronous to CLKOUT, exact start-up timing is guaranteed, allowing multiple processors to start synchronously and operate together in lock-step. When the RESET signal is deasserted, the initial chip operating mode is latched from the MODA, MODB, MODC, and MODD inputs. The RESET signal must be asserted after power up. Mode Select ANMODA is an active-low Schmitt-trigger input, internally synchronized to CLKOUT. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into the OMR when the RESET signal is deasserted. External Interrupt Request ANAfter reset, this signal becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. If IRQA is asserted synchronous to CLKOUT, multiple processors can be resynchronized using the WAIT instruction and asserting IRQA to exit the wait state. If the processor is in the stop standby state and IRQA is asserted, the processor exits the stop state. Freescale Semiconductor, Inc... RESET MODA Input Input IRQA 2-14 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Signal/Connection Descriptions Interrupt and Mode Control Table 2-9 Interrupt and Mode Control (Continued) Signal Name MODB Type Input State During Reset Input Signal Description Mode Select BNMODB is an active-low Schmitt-trigger input, internally synchronized to CLKOUT. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is deasserted. External Interrupt Request BNAfter hardware reset, this signal becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. If IRQB is asserted synchronous to CLKOUT, multiple processors can be resynchronized using the WAIT instruction and asserting IRQB to exit the wait state. Input Input Mode Select CNMODC is an active-low Schmitt-trigger input, internally synchronized to CLKOUT. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is deasserted. External Interrupt Request CNAfter hardware reset, this signal becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. If IRQC is asserted synchronous to CLKOUT, multiple processors can be resynchronized using the WAIT instruction and asserting IRQC to exit the wait state. Freescale Semiconductor, Inc... IRQB MODC IRQC MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 2-15 Freescale Semiconductor, Inc. Signal/Connection Descriptions Host Interface (HI08) Table 2-9 Interrupt and Mode Control (Continued) Signal Name MODD Type Input State During Reset Input Signal Description Mode Select DNMODD is an active-low Schmitt-trigger input, internally synchronized to CLKOUT. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is deasserted. External Interrupt Request DNAfter hardware reset, this signal becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. If IRQD is asserted synchronous to CLKOUT, multiple processors can be resynchronized using the WAIT instruction and asserting IRQD to exit the wait state. Freescale Semiconductor, Inc... IRQD 2.8 HOST INTERFACE (HI08) The HI08 provides a fast parallel 8-bit port, which can connect directly to the host bus. The HI08 supports a variety of standard buses and can be directly connected to a number of industry standard microcomputers, microprocessors, DSPs, and DMA hardware. 2.8.1 Host Port Usage Considerations When reading multiple-bit registers that are written by another asynchronous system, you must synchronize carefully. This problem commonly occurs when two asynchronous systems are connected (as they are in the host port). The considerations for proper operation are discussed in Table 2-10. 2-16 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Signal/Connection Descriptions Host Interface (HI08) Table 2-10 Host Port Usage Considerations Action Asynchronous read of receive byte registers Description When reading the receive byte registers, receive register high (RXH), receive register middle (RXM), or receive register low (RXL), use interrupts or poll the receive register data full (RXDF) flag which indicates that data is available. This assures that the data in the receive byte registers is valid. Do not write to the transmit byte registers, transmit register high (TXH), transmit register middle (TXM), or transmit register low (TXL), unless the transmit register data empty (TXDE) bit is set indicating that the transmit byte registers are empty. This guarantees that the transmit byte registers transfer valid data to the host receive (HRX) register. Change the host vector (HV) register only when the host command bit (HC) is clear. This guarantees that the DSP interrupt control logic receives a stable vector. Asynchronous write to transmit byte registers Freescale Semiconductor, Inc... Asynchronous write to host vector 2.8.2 Host Port Configuration The functions of the signals associated with the HI08 vary according to the programmed configuration of the interface as determined by the HI08 Port Control Register (HPCR). Refer to Section 6NHost Interface (HI08) for detailed descriptions of this and the other configuration registers used with the HI08. Host interface signal descriptions for the DSP56309 are listed in Table 2-11. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 2-17 Freescale Semiconductor, Inc. Signal/Connection Descriptions Host Interface (HI08) Table 2-11 Host Interface Signal Name H0H7 Type Input/ Output State During Reset Tri-stated Signal Description Host DataNWhen the HI08 is programmed to interface a non-multiplexed host bus and the HI function is selected, these signals are lines 07 of the data bidirectional, tri-state bus. Host AddressNWhen HI08 is programmed to interface a multiplexed host bus and the HI function is selected, these signals are lines 07 of the address/data bidirectional, multiplexed, tri-state bus. Port B 07NWhen the HI08 is configured as GPIO through the HPCR, these signals are individually programmed as inputs or outputs through the HI08 data direction register (HDDR). HA0 Input Input Host Address Input 0NWhen the HI08 is programmed to interface a non-multiplexed host bus and the HI function is selected, this signal is line 0 of the host address input bus. Host Address StrobeNWhen HI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is the host address strobe (HAS) Schmitt-trigger input. The polarity of the address strobe is programmable but is configured active-low (HAS) following reset. Port B 8NWhen the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. Freescale Semiconductor, Inc... HAD0 HAD7 Input/ Output PB0PB7 Input or Output HAS/HAS Input PB8 Input or Output 2-18 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Signal/Connection Descriptions Host Interface (HI08) Table 2-11 Host Interface (Continued) Signal Name HA1 Type Input State During Reset Input Signal Description Host Address Input 1NWhen the HI08 is programmed to interface a non-multiplexed host bus and the HI function is selected, this signal is line 1 of the host address (HA1) input bus. Host Address 8NWhen HI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 8 of the host address (HA8) input bus. Port B 9NWhen the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. Input Host Address Input 2NWhen the HI08 is programmed to interface a non-multiplexed host bus and the HI function is selected, this signal is line 2 of the host address (HA2) input bus. Host Address 9NWhen HI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 9 of the host address (HA9) input bus. Port B 10NWhen the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. Freescale Semiconductor, Inc... HA8 Input PB9 Input or Output HA2 Input HA9 Input PB10 Input or Output MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 2-19 Freescale Semiconductor, Inc. Signal/Connection Descriptions Host Interface (HI08) Table 2-11 Host Interface (Continued) Signal Name HRW Type Input State During Reset Input Signal Description Host Read/WriteNWhen HI08 is programmed to interface a single-data-strobe host bus and the HI function is selected, this signal is the host read/write (HRW) input. Host Read DataNWhen HI08 is programmed to interface a double-data-strobe host bus and the HI function is selected, this signal is the host read data strobe (HRD) Schmitt-trigger input. The polarity of the data strobe is programmable, but is configured as active-low (HRD) after reset. Port B 11NWhen the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. Input Host Data StrobeNWhen HI08 is programmed to interface a single-data-strobe host bus and the HI function is selected, this signal is the host data strobe (HDS) Schmitt-trigger input. The polarity of the data strobe is programmable, but is configured as active-low (HDS) following reset. Host Write DataNWhen HI08 is programmed to interface a double-data-strobe host bus and the HI function is selected, this signal is the host write data strobe (HWR) Schmitt-trigger input. The polarity of the data strobe is programmable, but is configured as active-low (HWR) following reset. Port B 12NWhen the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. Freescale Semiconductor, Inc... HRD/HRD Input PB11 Input or Output HDS/HDS Input HWR/ HWR Input PB12 Input or Output 2-20 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Signal/Connection Descriptions Host Interface (HI08) Table 2-11 Host Interface (Continued) Signal Name HCS Type Input State During Reset Input Signal Description Host Chip SelectNWhen HI08 is programmed to interface a non-multiplexed host bus and the HI function is selected, this signal is the host chip select (HCS) input. The polarity of the chip select is programmable, but is configured active-low (HCS) after reset. Host Address 10NWhen HI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 10 of the host address (HA10) input bus. Port B 13NWhen the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. Freescale Semiconductor, Inc... HA10 Input PB13 Input or Output MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 2-21 Freescale Semiconductor, Inc. Signal/Connection Descriptions Host Interface (HI08) Table 2-11 Host Interface (Continued) Signal Name HREQ/ HREQ Type Output State During Reset Input Signal Description Host RequestNWhen HI08 is programmed to interface a single host request host bus and the HI function is selected, this signal is the host request (HREQ) output. The polarity of the host request is programmable, but is configured as active-low (HREQ) following reset. The host request can be programmed as a driven or open-drain output. Transmit Host RequestNWhen HI08 is programmed to interface a double host request host bus and the HI function is selected, this signal is the transmit host request (HTRQ) output. The polarity of the host request is programmable, but is configured as active-low (HTRQ) following reset. The host request can be programmed as a driven or open-drain output. Port B 14NWhen the HI08 is programmed to interface a multiplexed host bus and the signal is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. Freescale Semiconductor, Inc... HTRQ/ HTRQ Output PB14 Input or Output 2-22 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Signal/Connection Descriptions Host Interface (HI08) Table 2-11 Host Interface (Continued) Signal Name HACK/ HACK Type Input State During Reset Input Signal Description Host AcknowledgeNWhen HI08 is programmed to interface a single host request host bus and the HI function is selected, this signal is the host acknowledge (HACK) Schmitt-trigger input. The polarity of the host acknowledge is programmable, but is configured as active-low (HACK) after reset. Receive Host RequestNWhen HI08 is programmed to interface a double host request host bus and the HI function is selected, this signal is the receive host request (HRRQ) output. The polarity of the host request is programmable, but is configured as active-low (HRRQ) after reset. The host request can be programmed as a driven or open-drain output. Port B 15NWhen the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. Freescale Semiconductor, Inc... HRRQ/ HRRQ Output PB15 Input or Output MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 2-23 Freescale Semiconductor, Inc. Signal/Connection Descriptions Enhanced Synchronous Serial Interface 2.9 ENHANCED SYNCHRONOUS SERIAL INTERFACE Two synchronous serial interfaces (ESSI0 and ESSI1) provide a full-duplex serial port for serial communication with a variety of serial devices, including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals which implement the Motorola SPI. 2.9.1 ESSI0 Freescale Semiconductor, Inc... The ESSI0 signal descriptions for the DSP56309 are listed in Table 2-12. Table 2-12 Enhanced Synchronous Serial Interface 0 (ESSI0) Signal Name SC00 Type Input or Output State During Reset Input Signal Description Serial Control 0NThe function of SC00 is determined by the selection of either synchronous or asynchronous mode. For asynchronous mode, this signal is used for the receive clock I/O (Schmitt-trigger input). For synchronous mode, this signal is used either for Transmitter 1 output or for Serial I/O Flag 0. This signal is driven by a weak keeper after reset. PC0 Port C 0NThe default configuration following reset is GPIO input PC0. When this port is configured as PC0, signal direction is controlled through the Port C direction register (PRR0). The signal can be configured as ESSI signal SC00 through the Port C control register (PCR0). 2-24 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Signal/Connection Descriptions Enhanced Synchronous Serial Interface Table 2-12 Enhanced Synchronous Serial Interface 0 (ESSI0) (Continued) Signal Name SC01 Type Input/ Output State During Reset Input Signal Description Serial Control 1NThe function of this signal is determined by the selection of either synchronous or asynchronous mode. For Asynchronous mode, this signal is the receiver frame sync I/O. For synchronous mode, this signal is used either for Transmitter 2 output or for Serial I/O Flag 1. This signal is driven by a weak keeper after reset. PC1 Input or Output Port C 1NThe default configuration following reset is GPIO input PC1. When this port is configured as PC1, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SC01 through PCR0. Input Serial Control Signal 2NSC02 is used for frame sync I/O. SC02 is the frame sync for both the transmitter and receiver in synchronous mode and for the transmitter only in asynchronous mode. When configured as an output, this signal is the internally generated frame sync signal. When configured as an input, this signal receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). This signal is driven by a weak keeper after reset. PC2 Input or Output Port C 2NThe default configuration following reset is GPIO input PC2. When this port is configured as PC2, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SC02 through PCR0. Freescale Semiconductor, Inc... SC02 Input/ Output MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 2-25 Freescale Semiconductor, Inc. Signal/Connection Descriptions Enhanced Synchronous Serial Interface Table 2-12 Enhanced Synchronous Serial Interface 0 (ESSI0) (Continued) Signal Name SCK0 Type Input/ Output State During Reset Input Signal Description Serial ClockNSCK0 is a bidirectional Schmitt-trigger input signal providing the serial bit rate clock for the ESSI interface. The SCK0 is a clock input or output used by both the transmitter and receiver in synchronous modes or by the transmitter in asynchronous modes. Although an external serial clock can be independent of and asynchronous to the DSP system clock, it must exceed the minimum clock cycle time of 6 T (i.e., the system clock frequency must be at least three times the external ESSI clock frequency). The ESSI needs at least three DSP phases inside each half of the serial clock. This signal is driven by a weak keeper after reset. PC3 Input or Output Port C 3NThe default configuration following reset is GPIO input PC3. When this port is configured as PC3, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SCK0 through PCR0. Input Serial Receive DataNSRD0 receives serial data and transfers the data to the ESSI receive shift register. SRD0 is an input when data is being received. This signal is driven by a weak keeper after reset. PC4 Input or Output Port C 4NThe default configuration following reset is GPIO input PC4. When this port is configured as PC4, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SRD0 through PCR0. Freescale Semiconductor, Inc... SRD0 Input/ Output 2-26 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Signal/Connection Descriptions Enhanced Synchronous Serial Interface Table 2-12 Enhanced Synchronous Serial Interface 0 (ESSI0) (Continued) Signal Name STD0 Type Input/ Output State During Reset Input Signal Description Serial Transmit DataNSTD0 is used for transmitting data from the serial Transmit shift register. STD0 is an output when data is being transmitted. This signal is driven by a weak keeper after reset. PC5 Input or Output Port C 5NThe default configuration following reset is GPIO input PC5. When this port is configured as PC5, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal STD0 through PCR0. Freescale Semiconductor, Inc... 2.9.2 ESSI1 The ESSI1 signal descriptions for the DSP56309 are listed in Table 2-13. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 2-27 Freescale Semiconductor, Inc. Signal/Connection Descriptions Enhanced Synchronous Serial Interface Table 2-13 Enhanced Synchronous Serial Interface 1 (ESSI1) Signal Name SC10 Type Input or Output State During Reset Input Signal Description Serial Control 0NThe function of SC10 is determined by the selection of either synchronous or asynchronous mode. For asynchronous mode, this signal is used for the receive clock I/O (Schmitt-trigger input). For synchronous mode, this signal is used either for Transmitter 1 output or for Serial I/O Flag 0. This signal is driven by a weak keeper after reset. PD0 Port D 0NThe default configuration following reset is GPIO input PD0. When this port is configured as PD0, signal direction is controlled through the Port D direction register (PRR1). The signal can be configured as an ESSI signal SC10 through the Port D control register (PCR1). Input/ Output Input Serial Control 1NThe function of this signal is determined by the selection of either synchronous or asynchronous mode. For asynchronous mode, this signal is the receiver frame sync I/O. For synchronous mode, this signal is used either for Transmitter 2 output or for Serial I/O Flag 1. This signal is driven by a weak keeper after reset. PD1 Input or Output Port D 1NThe default configuration following reset is GPIO input PD1. When this port is configured as PD1, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SC11 through PCR1. Freescale Semiconductor, Inc... SC11 2-28 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Signal/Connection Descriptions Enhanced Synchronous Serial Interface Table 2-13 Enhanced Synchronous Serial Interface 1 (ESSI1) (Continued) Signal Name SC12 Type Input/ Output State During Reset Input Signal Description Serial Control Signal 2NSC12 is used for frame sync I/O. SC12 is the frame sync for both the transmitter and receiver in synchronous mode and for the transmitter only in asynchronous mode. When configured as an output, this signal is the internally generated frame sync signal. When configured as an input, this signal receives an external frame sync signal for the transmitter. The receiver receives an external frame sync signal as well when in synchronous operation). This signal is driven by a weak keeper after reset. Port D 2NThe default configuration following reset is GPIO input PD2. When this port is configured as PD2, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SC12 through PCR1. Freescale Semiconductor, Inc... PD2 Input or Output MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 2-29 Freescale Semiconductor, Inc. Signal/Connection Descriptions Enhanced Synchronous Serial Interface Table 2-13 Enhanced Synchronous Serial Interface 1 (ESSI1) (Continued) Signal Name SCK1 Type Input/ Output State During Reset Input Signal Description Serial ClockNSCK1 is a bidirectional Schmitt-trigger input signal providing the serial bit rate clock for the ESSI interface. The SCK1 is a clock input or output used by both the transmitter and receiver in synchronous modes or by the transmitter in asynchronous modes. Although an external serial clock can be independent of and asynchronous to the DSP system clock, it must exceed the minimum clock cycle time of 6T (i.e., the system clock frequency must be at least three times the external ESSI clock frequency). The ESSI needs at least three DSP phases inside each half of the serial clock. This signal is driven by a weak keeper after reset. PD3 Input or Output Port D 3NThe default configuration following reset is GPIO input PD3. When this port is configured as PD3, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SCK1 through PCR1. Input Serial Receive DataNSRD1 receives serial data and transfers the data to the ESSI receive shift register. SRD1 is an input when data is being received. This signal is driven by a weak keeper after reset. PD4 Input or Output Port D 4NThe default configuration following reset is GPIO input PD4. When this port is configured as PD4, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SRD1 through PCR1. Freescale Semiconductor, Inc... SRD1 Input/ Output 2-30 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Signal/Connection Descriptions Enhanced Synchronous Serial Interface Table 2-13 Enhanced Synchronous Serial Interface 1 (ESSI1) (Continued) Signal Name STD1 Type Input/ Output State During Reset Input Signal Description Serial Transmit DataNSTD1 is used for transmitting data from the serial transmit shift register. STD1 is an output when data is being transmitted. This signal is driven by a weak keeper after reset. PD5 Input or Output Port D 5NThe default configuration following reset is GPIO input PD5. When this port is configured as PD5, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal STD1 through PCR1. Freescale Semiconductor, Inc... MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 2-31 Freescale Semiconductor, Inc. Signal/Connection Descriptions Serial Communication Interface (SCI) 2.10 SERIAL COMMUNICATION INTERFACE (SCI) SCI provides a full duplex port for serial communication to other DSPs, microprocessors, or peripherals such as modems. SCI signal descriptions are listed in Table 2-14. Table 2-14 Serial Communication Interface (SCI) Signal Name Type Input State During Reset Input Signal Description Serial Receive DataNThis input receives byte oriented serial data and transfers it to the SCI receive shift register. This signal is driven by a weak keeper after reset. PE0 Input or Output Port E 0NThe default configuration following reset is GPIO input PE0. When this port is configured as PE0, signal direction is controlled through the SCI Port E direction register (PRR). The signal can be configured as an SCI signal RXD through the SCI Port E control register (PCR). Input Serial Transmit DataNThis signal transmits data from SCI transmit data register. This signal is driven by a weak keeper after reset. PE1 Input or Output Port E 1NThe default configuration following reset is GPIO input PE1. When this port is configured as PE1, signal direction is controlled through the SCI PRR. The signal can be configured as an SCI signal TXD through the SCI PCR. Freescale Semiconductor, Inc... RXD TXD Output 2-32 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Signal/Connection Descriptions Timers Table 2-14 Serial Communication Interface (SCI) (Continued) Signal Name SCLK Type Input/ Output State During Reset Input Signal Description Serial ClockNThis is the bidirectional Schmitt-trigger input signal providing the input or output clock used by the transmitter and/or the receiver. This signal is driven by a weak keeper after reset. PE2 Input or Output Port E 2NThe default configuration following reset is GPIO input PE2. When this port is configured as PE2, signal direction is controlled through the SCI PRR. The signal can be configured as an SCI signal SCLK through the SCI PCR. Freescale Semiconductor, Inc... 2.11 TIMERS Three identical and independent timers are implemented in the DSP56309. Each timer can use internal or external clocking; each timer can interrupt the DSP56309 after a specified number of events (clocks) or can signal an external device after counting a specific number of internal events. Triple timer signal descriptions are listed in Table 2-15. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 2-33 Freescale Semiconductor, Inc. Signal/Connection Descriptions Timers Table 2-15 Triple Timer Signals Signal Name TIO0 Type Input or Output State During Reset Input Signal Description Timer 0 Schmitt-Trigger Input/OutputN When timer 0 functions as an external event counter or in measurement mode, TIO0 is used as input. When timer 0 functions in watchdog, timer, or pulse modulation mode, TIO0 is used as output. This signal is driven by a weak keeper after reset. The default mode after reset is GPIO input. This can be changed to output or configured as a timer input/output through the timer 0 control/status register (TCSR0). TIO1 Input or Output Input Timer 1 Schmitt-Trigger Input/OutputN When Timer 1 functions as an external event counter or in measurement mode, TIO1 is used as input. When timer 1 functions in watchdog, timer, or pulse modulation mode, TIO1 is used as output. This signal is driven by a weak keeper after reset. The default mode after reset is GPIO input. This can be changed to output or configured as a timer input/output through the timer 1 control/status register (TCSR1). Freescale Semiconductor, Inc... 2-34 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Signal/Connection Descriptions OnCE/JTAG Interface Table 2-15 Triple Timer Signals (Continued) Signal Name TIO2 Type Input or Output State During Reset Input Signal Description Timer 2 Schmitt-Trigger Input/OutputN When Timer 2 functions as an external event counter or in measurement mode, TIO2 is used as input. When timer 2 functions in watchdog, timer, or pulse modulation mode, TIO2 is used as output. This signal is driven by a weak keeper after reset. The default mode after reset is GPIO input. This can be changed to output or configured as a timer input/output through the timer 2 control/status register (TCSR2). Freescale Semiconductor, Inc... 2.12 OnCE/JTAG INTERFACE OnCE/JTAG interface signal descriptions are listed in Table 2-16. Table 2-16 OnCE/JTAG Interface Signal Name TCK Type Input State During Reset Input Signal Description Test ClockNTCK is a test clock input signal used to synchronize the JTAG test logic. Its pin has a pull-up resistor. Test Data InputNTDI is a test data serial input signal used for test instructions and data. TDI is sampled on the rising edge of TCK and has an internal pull-up resistor. TDI Input Input MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 2-35 Freescale Semiconductor, Inc. Signal/Connection Descriptions OnCE/JTAG Interface Table 2-16 OnCE/JTAG Interface (Continued) Signal Name TDO Type Output State During Reset Tri-stated Signal Description Test Data OutputNTDO is a test data serial output signal used for test instructions and data. TDO is tri-statable and is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCK. Test Mode SelectNTMS is an input signal used to sequence the test controllerOs state machine. TMS is sampled on the rising edge of TCK and has an internal pull-up resistor. Test ResetNTRST is an active-low Schmitt-trigger input signal used to asynchronously initialize the test controller. TRST has an internal pull-up resistor. TRST must be asserted after power up. Freescale Semiconductor, Inc... TMS Input Input TRST Input Input 2-36 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Signal/Connection Descriptions OnCE/JTAG Interface Table 2-16 OnCE/JTAG Interface (Continued) Signal Name DE Type Input/ Output State During Reset Input Signal Description Debug EventNDE is an open-drain, bidirectional, active-low signal providing, as an input, a means of entering debug mode of operation from an external command controller, and as an output, a means of acknowledging that the chip has entered debug mode. This signal, when asserted as an input, causes the DSP56300 core to finish the current instruction being executed, save the instruction pipeline information, enter debug mode, and wait for commands to be entered from the debug serial input line. This signal is asserted as an output for three clock cycles when the chip enters debug mode as a result of a debug request or as a result of meeting a breakpoint condition. The DE has an internal pull-up resistor. This is not a standard part of the JTAG TAP controller. The signal connects directly to the OnCE module to initiate debug mode directly or to provide a direct external indication that the chip has entered debug mode. All other interfacing with the OnCE module must occur through the JTAG port. Freescale Semiconductor, Inc... MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 2-37 Freescale Semiconductor, Inc. Signal/Connection Descriptions OnCE/JTAG Interface Freescale Semiconductor, Inc... 2-38 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. SECTION 3 MEMORY CONFIGURATION Freescale Semiconductor, Inc... MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 3-1 Freescale Semiconductor, Inc. Memory Configuration 3.1 3.2 3.3 3.4 3.5 MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 RAM CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 MEMORY CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . 3-7 MEMORY MAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 INTERNAL I/O MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . 3-18 Freescale Semiconductor, Inc... 3-2 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Memory Configuration Memory Spaces 3.1 MEMORY SPACES The DSP56309 provides three independent memory spaces: Program X data Y data Each memory space uses 24-bit addressing by default. The program and data word length is 24 bits. Moreover, this device supports remapping address attribute registers Oon the fly,O thus allowing access to 16 M of memory. The DSP56309 provides a sixteen-bit compatibility mode that effectively uses 16-bit addressing for each memory space, allowing access to 64K each of memory. This mode puts zeroes in the most significant byte of the usual (24-bit) program and data word; it ignores the zeroed byte, thus effectively using 16-bit program and data words. The sixteen-bit compatibility mode allows the DSP56309 to use 56000 object code without change, thus minimizing system cost for applications that use the smaller address space. See the DSP56300 Family Manual for further information. Freescale Semiconductor, Inc... 3.1.1 Program Memory Space Program memory space consists of the following: Internal program memory (Program RAM, 20K by default) Bootstrap Program ROM (192 x 24-bit) (Optionally) off-chip memory expansion (as much as 16 M in 24-bit mode and 64K in 16-bit mode) (Optionally) instruction cache (1K) formed from Program RAM Program memory space at locations $FF00C0 to $FFFFFF is reserved and should not be accessed. 3.1.2 Data Memory Spaces Data memory space is divided into X data memory and Y data memory to match the natural partitioning of DSP algorithms. The data memory partitioning allows the MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 3-3 Freescale Semiconductor, Inc. Memory Configuration Memory Spaces DSP56309 to feed two operands to the Data ALU simultaneously, enabling it to perform a multiply-accumulate operation in one clock cycle. X and Y data memory are identical in structure and functionality except for the upper 128 words of each space. The upper 128 words of X data memory are reserved for internal I/O. We recommend that the programmer reserve the upper 128 words of Y data memory for external I/O. (For further information, see Section 3.1.2.1 X Data Memory Space and Section 3.1.2.2 Y Data Memory Space.) X and Y data memory space each consist of the following: Freescale Semiconductor, Inc... Internal data memory (X data RAM and Y data RAM, the default size of each is 7K, but they can be switched to 5K each) (Optionally) Off-chip memory expansion (up to 16 M in the 24-bit address mode and 64K in the 16-bit address mode) 3.1.2.1 X Data Memory Space The on-chip peripheral registers and some of the DSP56309 core registers occupy the top 128 locations of X data memory ($FFFF80$FFFFFF in the 24-bit Address mode or $FF80$FFFF in the 16-bit Address mode). This area is called X-I/O space, and it can be accessed by MOVE and MOVEP instructions and by bit oriented instructions (BCHG, BCLR, BSET, BTST, BRCLR, BRSET, BSCLR, BSSET, JCLR, JSET, JSCLR, and JSSET). For a listing of the contents of this area, see the programming sheets in Appendix DNProgramming Reference. The X memory space at locations $FF0000 to $FFEFFF is reserved and should not be accessed by the programmer. 3.1.2.2 Y Data Memory Space The off-chip peripheral registers should be mapped into the top 128 locations of Y data memory ($FFFF80$FFFFFF in the 24-bit address mode or $FF80$FFFF in the 16-bit address mode) to take advantage of the move peripheral data (MOVEP) instruction and the bit oriented instructions (BCHG, BCLR, BSET, BTST, BRCLR, BRSET, BSCLR, BSSET, JCLR, JSET, JSCLR, and JSSET). The Y memory space at locations $FF0000 to $FFEFFF is reserved and should not be accessed by the programmer. 3-4 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Memory Configuration RAM Configuration 3.1.3 Memory Space Configuration Memory space addressing is 24-bit by default. The DSP56309 switches to sixteen-bit address compatibility mode by setting the sixteen-bit compatibility (SC) bit in the Status Register (SR). Table 3-1 Memory Space Configuration Bit Settings for the DSP56309 Bit Abbreviation Bit Name Sixteen-bit Compatibility Bit Location SR 13 Cleared = 0 Effect (Default) 16M word address space (24-bit address) Set = 1 Effect 64K word address space (16-bit address) Freescale Semiconductor, Inc... SC Memory maps for the different configurations are shown in Figure 3-1 through Figure 3-8. 3.2 RAM CONFIGURATION The DSP56309 contains 34K of RAM, divided by default into the following: Program RAM (20K) X data RAM (7K) Y data RAM (7K) RAM configuration depends on two bits: the Cache Enable (CE) of the SR and the Memory Select (MS) of the Operating Mode Register (OMR). Table 3-2 RAM Configuration Bit Settings for the DSP56309 Bit Abbreviation CE MS Bit Name Cache Enable Memory Switch Bit Location SR 19 OMR 7 Cleared = 0 Effect (Default) Cache Disabled Program RAM 20K X data RAM 7K Y data RAM 7K Set = 1 Effect Cache Enabled 1K Program RAM 24K X data RAM 5K Y data RAM 5K MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 3-5 Freescale Semiconductor, Inc. Memory Configuration RAM Configuration Memory maps for the different configurations are shown in Figure 3-1 through Figure 3-8. Note: The MS bit cannot be changed when CE is set. The instruction cache occupies the top 1K of what would otherwise be Program RAM; if you switch memory into or out of Program RAM when the cache is enabled, the switch causes conflicts. To change the MS bit when CE is set, do the following: 1. Clear CE. 2. Change MS. Freescale Semiconductor, Inc... 3. Set CE. 3.2.1 On-Chip Program Memory (Program RAM) The on-chip Program RAM consists of 24-bit wide, high-speed, internal Static RAM occupying the lowest 20K (default), 23K, 24K, or 19K locations in the program memory space (depending on the settings of the MS and CE bits). The Program RAM default organization is 80 banks of 256 24-bit words (20K). The upper eight banks of both X data RAM and Y data RAM can be configured as Program RAM by setting the MS bit. When the CE is set, the upper 1K of Program RAM is used as an internal Instruction Cache. CAUTION While the contents of Program RAM are unaffected by toggling the MS bit, the location of program data placed in the Program RAM/Instruction Cache area changes after the MS bit is toggled, since the cache always occupies the top-most 1K Program RAM addresses. To preserve program data integrity, do not set or clear the MS bit when the CE bit is set. See Section 3.2 on page 3-5 for the correct procedure. 3.2.2 On-Chip X Data Memory (X Data RAM) The on-chip X data RAM consists of 24-bit wide, high-speed, internal Static RAM occupying the lowest 7K (default) or 5K locations in the X memory space. The size of the X data RAM depends on the setting of the MS bit (default: MS is cleared). The X data RAM default organization is 28 banks of 256 (7K) 24-bit words. Eight banks of RAM can be switched from the X data RAM to the Program RAM by setting the MS bit (leaving 5K of X data RAM). 3-6 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Memory Configuration Memory Configurations 3.2.3 On-Chip Y Data Memory (Y Data RAM) The on-chip Y data RAM consists of 24-bit wide, high-speed, internal Static RAM occupying the lowest 7K (default) or 5K locations in the Y memory space. The size of the Y data RAM is dependent on the setting of the MS bit (default: MS is cleared). The Y data RAM default organization is 28 banks of 256 (7K) 24-bit words. Eight banks of RAM can be switched from the Y data RAM to the Program RAM by setting the MS bit (leaving 5K of Y data RAM). Freescale Semiconductor, Inc... 3.2.4 Bootstrap ROM The bootstrap code is accessed at addresses $FF0000 to $FFF0BF (192 words) in program memory space. The bootstrap ROM cannot be accessed in 16-bit address compatibility mode. See Appendix ANBootstrap Programs for a complete listing of the bootstrap code. 3.3 MEMORY CONFIGURATIONS Memory configuration determines the size and address range for addressable memory, as well as the amount of memory allocated to Program RAM, data RAM, and the instruction cache. 3.3.1 Memory Space Configurations The memory space configurations are listed in Table 3-3. Table 3-3 Memory Space Configurations for the DSP56309 SC Bit Setting 0 1 Addressable Memory Size 16M words 64K words Address Range $000000 $FFFFFF $0000$FFFF Number of Address Bits 24 16 MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 3-7 Freescale Semiconductor, Inc. Memory Configuration Memory Configurations 3.3.2 RAM Configurations The RAM configurations for the DSP56309 appear in Table 3-4. Table 3-4 RAM Configurations for the DSP56309 Bit Settings MS CE 0 1 0 1 Program RAM 20 19 24 23 Memory Sizes (in K) X data RAM 7 7 5 5 Y data RAM 7 7 5 5 Cache 0 1 0 1 Freescale Semiconductor, Inc... 0 0 1 1 The actual memory locations for Program RAM and the instruction cache in the Program memory space are determined by the MS and CE bits. Their addresses appear in Table 3-5. Table 3-5 Memory Locations for Program RAM and Instruction Cache MS 0 0 1 1 CE 0 1 0 1 Program RAM Location $0000$4FFF $0000$4BFF $0000$5FFF $0000$5BFF Cache Location N/A $4C00$4FFF N/A $5C00$5FFF 3-8 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Memory Configuration Memory Maps The actual memory locations for both X and Y data RAM in their own memory space are determined by the MS bit. Their addresses appear in Table 3-6. Table 3-6 Memory Locations for Data RAM MS 0 1 Data RAM Location $0000$1BFF $0000$13FF Freescale Semiconductor, Inc... 3.4 MEMORY MAPS Figure 3-1 through Figure 3-8 illustrate each of the memory space and RAM configurations defined by the settings of the SC, MS, and CE bits. The figures show the configuration, and the accompanying tables show the bit settings, memory sizes, and memory locations. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 3-9 Freescale Semiconductor, Inc. Memory Configuration Memory Maps Program X Data Y Data $FFFFFF Internal Reserved $FFFFFF $FFFF80 $FFF000 Internal I/O External Internal Reserved $FFFFFF $FFFF80 $FFF000 External I/O External Internal Reserved Freescale Semiconductor, Inc... $FFF0C0 Bootstrap ROM $FF0000 $FF0000 External $005000 Internal $001C00 Program RAM 20K $000000 $000000 External $FF0000 External $001C00 Internal X data RAM 7K $000000 Internal Y data RAM 7K Bit Settings SC 0 MS 0 CE 0 Program RAM 20K $0000$4FFF Memory Configuration X Data RAM 7K $0000$1BFF Y Data RAM 7K $0000$1BFF Cache None Addressable Memory Size 16M AA0557 Figure 3-1 Default Settings (0, 0, 0) 3-10 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Memory Configuration Memory Maps Program X Data Y Data $FFFFFF Internal Reserved $FFFFFF $FFFF80 $FFF000 Internal I/O External Internal Reserved $FFFFFF $FFFF80 $FFF000 External I/O External Internal Reserved Freescale Semiconductor, Inc... $FFF0C0 Bootstrap ROM $FF0000 $FF0000 External $005000 $004C00 External I-Cache 1K Internal Program RAM 19K $000000 $001C00 Internal X data RAM 7K $FF0000 External $001C00 Internal Y data RAM 7K $000000 $000000 Bit Settings SC 0 MS 0 CE 1 Program RAM 19K $0000 $4BFF Memory Configuration X Data RAM 7K $0000 $1BFF Y Data RAM 7K $0000 $1BFF Cache 1K $4C00 $4FFF Addressable Memory Size 16 M AA0561 Figure 3-2 Instruction Cache Enabled (0, 0, 1) MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 3-11 Freescale Semiconductor, Inc. Memory Configuration Memory Maps Program X Data Y Data $FFFFFF Internal Reserved $FFFFFF $FFFF80 $FFF000 Internal I/O External Internal Reserved $FFFFFF $FFFF80 $FFF000 External I/O External Internal Reserved Freescale Semiconductor, Inc... $FFF0C0 Bootstrap ROM $FF0000 $FF0000 External External $FF0000 External $006000 $001400 Internal X data RAM 5K $000000 $001400 Internal Y data RAM 5K $000000 Internal Program RAM 24K $000000 Bit Settings SC 0 MS 1 CE 0 Program RAM 24K $0000 $5FFF Memory Configuration X Data RAM 5K $0000 $13FF Y Data RAM 5K $0000 $13FF Cache None Addressable Memory Size 16 M AA0559 Figure 3-3 Switched Program RAM (0, 1, 0) 3-12 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Memory Configuration Memory Maps Program X Data Y Data $FFFFFF Internal Reserved $FFFFFF $FFFF80 $FFF000 Internal I/O External Internal Reserved $FFFFFF $FFFF80 $FFF000 External I/O External Internal Reserved Freescale Semiconductor, Inc... $FFF0C0 Bootstrap ROM $FF0000 $FF0000 External $006000 $005C00 $001400 I-Cache 1K Internal Program RAM 23K Internal X data RAM 5K $000000 External $FF0000 External $001400 Internal Y data RAM 5K $000000 $000000 Bit Settings SC 0 MS 1 CE 1 Program RAM 23K $0000 $5BFF Memory Configuration X Data RAM 5K $0000 $13FF Y Data RAM 5K $0000 $13FF Cache 1K $5C00 $5FFF Addressable Memory Size 16 M AA0563 Figure 3-4 Switched Program RAM and Instruction Cache Enabled (0, 1, 1) MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 3-13 Freescale Semiconductor, Inc. Memory Configuration Memory Maps Program X Data Y Data $FFFF $FFFF $FF80 Internal I/O $FFFF $FF80 External I/O External External External Freescale Semiconductor, Inc... $5000 Internal Program RAM 20K $1C00 Internal X data RAM 7K $0000 $1C00 Internal Y data RAM 7K $0000 $0000 Bit Settings SC 1 MS 0 CE 0 Program RAM 20K $0000 $4FFF Memory Configuration X Data RAM 7K $0000 $1BFF Y Data RAM 7K $0000 $1BFF Cache None Addressable Memory Size 64K AA0558 Figure 3-5 16-bit Space with Default RAM (1, 0, 0) 3-14 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Memory Configuration Memory Maps Program X Data Y Data $FFFF $FFFF $FF80 External Internal I/O $FFFF $FF80 External I/O External External Freescale Semiconductor, Inc... $5000 $4C00 I-Cache 1K $1C00 Internal Program RAM 19K Internal X data RAM 7K $0000 $0000 $1C00 Internal Y data RAM 7K $0000 Bit Settings SC 1 MS 0 CE 1 Program RAM 19K $0000 $4BFF Memory Configuration X Data RAM 7K $0000 $1BFF Y Data RAM 7K $0000 $1BFF Cache 1K $4C00 $4FFF Addressable Memory Size 64K AA0562 Figure 3-6 16-bit Space with Instruction Cache Enabled (1, 0, 1) MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 3-15 Freescale Semiconductor, Inc. Memory Configuration Memory Maps Program X Data Y Data $FFFF $FFFF $FF80 Internal I/O $FFFF $FF80 External I/O External External External Freescale Semiconductor, Inc... $1400 $6000 Internal Program RAM 24K $0000 $0000 $1400 Internal X data RAM 5K $0000 Internal Y data RAM 5K Bit Settings SC 1 MS 1 CE 0 Program RAM 24K $0000 $5FFF Memory Configuration X Data RAM 5K $0000 $13FF Y Data RAM 5K $0000 $13FF Cache None Addressable Memory Size 64K AA0560 Figure 3-7 16-bit Space with Switched Program RAM (1, 1, 0) 3-16 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Memory Configuration Memory Maps Program X Data Y Data $FFFF $FFFF $FF80 Internal I/O $FFFF $FF80 External I/O External External External Freescale Semiconductor, Inc... $6000 I-Cache 1K $5C00 $0000 Internal Program RAM 23K $1400 Internal X data RAM 5K $0000 $1400 Internal Y data RAM 5K $0000 Bit Settings SC 1 MS 1 CE 1 Program RAM 23K $0000 $5FFF Memory Configuration X Data RAM 5K $0000 $13FF Y Data RAM 5K $0000 $13FF Cache 1K $5C00 $5FFF Addressable Memory Size 64K AA0564 Figure 3-8 16-bit Space, Switched Program RAM, Instruction Cache Enabled (1, 1, 1) MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 3-17 Freescale Semiconductor, Inc. Memory Configuration Internal I/O Memory Map 3.5 INTERNAL I/O MEMORY MAP The DSP56309 internal X-I/O space (the top 128 locations of the X data memory space) is listed in Table D-2 on page D-11 of Appendix DNInterrupt Sources. Freescale Semiconductor, Inc... 3-18 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. SECTION 4 CORE CONFIGURATION Freescale Semiconductor, Inc... MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 4-1 Freescale Semiconductor, Inc. Core Configuration Freescale Semiconductor, Inc... 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 BOOTSTRAP PROGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 INTERRUPT SOURCES AND PRIORITIES . . . . . . . . . . . . . 4-9 DMA REQUEST SOURCES . . . . . . . . . . . . . . . . . . . . . . . . 4-16 OPERATING MODE REGISTER (OMR). . . . . . . . . . . . . . . 4-17 PLL CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . 4-18 DEVICE IDENTIFICATION REGISTER (IDR). . . . . . . . . . . 4-18 AA CONTROL REGISTERS (AAR0AAR3) . . . . . . . . . . . . 4-19 JTAG BOUNDARY SCAN REGISTER (BSR) . . . . . . . . . . . 4-20 4-2 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Core Configuration Introduction 4.1 INTRODUCTION This chapter presents details on core configuration specific to the DSP56309. These configuration details include the following: Operating modes Bootstrap program Interrupt sources and priorities DMA request sources Freescale Semiconductor, Inc... Operating Mode Register PLL control register AA control registers JTAG Boundary Scan Register For information on specific registers or modules in the DSP56300 core, refer to the DSP56300 Family Manual (DSP56300FM/AD). 4.2 OPERATING MODES The DSP56309 begins operation by leaving Reset state and going into one of eight operating modes. As the DSP56309 exits the Reset state, it loads the values of MODA, MODB, MODC, and MODD into bits MA, MB, MC, and MD of the Operating Mode Register (OMR). These bit settings select the operating mode, which determines the bootstrap program option the microprocessor uses to start up. The MAMD bits of the OMR can also be set directly by software. A jump directly to the bootstrap program entry point ($FF0000) after the OMR bits are set causes the DSP56309 to execute the specified bootstrap program option (except modes 0 and 8). Table 4-1 shows the DSP56309 bootstrap operation modes, the corresponding settings of the external operational mode signal lines (the mode bits MAMD in the OMR), and the reset vector address to which the DSP56309 jumps once it leaves the Reset state. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 4-3 Freescale Semiconductor, Inc. Core Configuration Bootstrap Program 4.3 BOOTSTRAP PROGRAM Bootstrap operating mode descriptions for the DSP56309 are listed in Table 4-1. Table 4-1 DSP56309 Operating Modes Mode 0 MODD 0 MODC 0 MODB 0 MODA 0 Reset Vector $C00000 Description Expanded mode: address $C00000 is reflected as $00000 on Port A signals A0-A17 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Expanded mode Boot from byte-wide memory at $D00000 Boot through SCI Reserved HI08 boot in ISA mode HI08 boot in HC11 non-multiplexed mode HI08 boot in 8051 multiplexed bus mode HI08 boot in MC68302 mode Freescale Semiconductor, Inc... 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 $FF0000 $FF0000 $FF0000 $FF0000 $FF0000 $FF0000 $FF0000 $008000 $FF0000 $FF0000 $FF0000 $FF0000 $FF0000 $FF0000 $FF0000 The bootstrap program is factory-programmed in an internal, 192-word by 24-bit bootstrap ROM located in program memory space at locations $FF0000$FF00BF. The bootstrap program can load any Program RAM segment from an external byte-wide EPROM, the SCI, or the host port. The bootstrap program code is listed in Appendix ANBootstrap Programs. 4-4 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Core Configuration Bootstrap Program On exiting the reset state, the DSP56309 does the following: 1. Samples the MODA, MODB, MODC, and MODD signal lines. 2. Loads their values into bits MA, MB, MC, and MD in the OMR. The contents of the MA, MB, MC, and MD bits determine which bootstrap mode the DSP56309 enters: 1. If MA, MB, MC, and MD are all cleared (Bootstrap mode 0), the program bypasses the bootstrap ROM, and the DSP56309 starts loading instructions from external program memory location $C00000. Freescale Semiconductor, Inc... 2. If MA, MB, and MC are cleared and MD is set (Bootstrap mode 8), the program bypasses the bootstrap ROM, and the DSP56309 starts loading in instruction values from external program memory location $008000. 3. Otherwise (Bootstrap modes 17), the DSP56309 jumps to the bootstrap program entry point at $FF0000. If the bootstrap program is loading via the host interface (HI08), setting the HF0 bit in the host status register (HSR) causes the DSP56309 to stop loading and begin executing the loaded program at the specified start address. See Table 4-1 for a tabular description of the mode bit settings for the operating modes. The bootstrap program options (except modes 0 and 8) can be invoked at any time by setting the MA, MB, MC, and MD bits in the OMR and jumping to the bootstrap program entry point, $FF0000. Software can directly set the mode selection bits in the OMR. Bootstrap modes 0 and 8 are the normal functioning modes for the DSP56309. Bootstrap modes 17 are the bootstrap modes proper. Bootstrap modes 9, A, C, D, E, F select different, specific devices for loading the bootstrap source. In those bootstrap modes, the bootstrap program expects the following data sequence when downloading the user program through an external port: 1. Three bytes defining the number of (24-bit) program words to be loaded 2. Three bytes defining the (24-bit) start address to which the user program loads in the DSP56309 program memory 3. The user program (three bytes for each 24-bit program word) MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 4-5 Freescale Semiconductor, Inc. Core Configuration Bootstrap Program The three bytes for each data sequence must be loaded with the least significant byte first. Once the bootstrap program completes loading the specified number of words, it jumps to the specified starting address and executes the loaded program. 4.3.1 Mode Mode 0: Expanded Mode MODD 0 MODC 0 MODB 0 MODA 0 Reset Vector $C00000 Description Expanded mode Freescale Semiconductor, Inc... 0 The bootstrap ROM is bypassed and the DSP56309 starts fetching instructions beginning at address $C00000. Memory accesses are performed using SRAM memory access type with 31 wait states and no address attributes selected (by default). 4.3.2 Modes 1 to 7: Reserved These modes are reserved for future use. 4.3.3 Mode 8 Mode 8: Expanded Mode MODD 1 MODC 0 MODB 0 MODA 0 Reset Vector $008000 Description Expanded mode The bootstrap ROM is bypassed and the DSP56309 starts fetching instructions beginning at address $008000. Memory accesses are performed using SRAM memory access type with 31 wait states and no address attributes selected. 4-6 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Core Configuration Bootstrap Program 4.3.4 Mode 9 Mode 9: Boot from Byte-Wide External Memory MODD 1 MODC 0 MODB 0 MODA 1 Reset Vector $FF0000 Description Boot from byte-wide memory (at $D00000) Freescale Semiconductor, Inc... The bootstrap program loads instructions through Port A from external byte-wide memory, starting at P:$D00000. The SRAM memory access type is selected by the values in address attribute register 1 (AAR1). Thirty-one wait states are inserted between each memory access. Address $D00000 is reflected as address $00000 on Port A signals HA0-HA17. 4.3.5 Mode A Mode A: Boot from SCI MODD 1 MODC 0 MODB 1 MODA 0 Reset Vector $FF0000 Description Boot through SCI Instructions are loaded through the SCI. The bootstrap program sets the SCI to operate in 10-bit asynchronous mode, with one start bit, eight data bits, one stop bit and no parity. Data is received in this order; start bit, eight data bits (LSB first), and one stop bit. Data is aligned in the SCI receive data register with the LSB of the least significant byte of the received data appearing at bit 0. The user must provide an external clock source with a frequency at least 16 times the transmission data rate. Each byte received by the SCI is echoed back through the SCI transmitter to the external transmitter. 4.3.6 Mode B Mode B: Reserved MODD 1 MODC 0 MODB 1 MODA 1 Reset Vector $FF0000 Description Reserved This mode is reserved for future use. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 4-7 Freescale Semiconductor, Inc. Core Configuration Bootstrap Program 4.3.7 Modes C, D, E, F: Boot from HI08 Modes C, D, E, and F enable the programmer to boot through the host interface (HI08) in various ways. 4.3.7.1 Mode C Mode C: In ISA/DSP5630X Mode (8-Bit Bus) MODD 1 MODC 1 MODB 0 MODA 0 Reset Vector $FF0000 Description HI08 Bootstrap in ISA/DSP5630X Freescale Semiconductor, Inc... In mode C: boot from HI08 in ISA/DSP5630x with an 8-bit wide bus, the HI08 is configured to interface with an ISA bus or with the memory expansion port of a master DSP5630n processor. If the host processor sets host flag 0 (HF0) in the HI08 interface control register (HCR) while writing the initialization program, the bootstrap program stops loading instructions, jumps to the starting address specified, and executes the loaded program. 4.3.7.2 Mode D Mode D: In HC11 Non-multiplexed Mode MODD 1 MODC 1 MODB 0 MODA 1 Reset Vector $FF0000 Description HI08 Bootstrap in HC11 non-multiplexed In mode D: boot from HI08 in HC11 non-multiplexed mode, the bootstrap program sets the host interface to interface with the Motorola HC11 microcontroller. If the host processor sets host flag 0 (HF0) in the HCR while writing the initialization program, the bootstrap program stops loading instructions, jumps to the starting address specified, and executes the loaded program. 4-8 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Core Configuration Interrupt Sources and Priorities 4.3.7.3 Mode E Mode E: In 8051 Multiplexed Bus Mode MODD 1 MODC 1 MODB 1 MODA 0 Reset Vector $FF0000 Description HI08 Bootstrap in 8051 multiplexed bus In mode E: boot from HI08 in 8051 multiplexed bus mode, the bootstrap program sets the host interface to interface with the IntelO 8051 bus. Freescale Semiconductor, Inc... If the host processor sets host flag 0 (HF0) in the HCR while writing the initialization program, the bootstrap program stops loading instructions, jumps to the starting address specified, and executes the loaded program. 4.3.7.4 Mode F Mode F: In 68302/68360 Bus Mode MODD 1 MODC 1 MODB 1 MODA 1 Reset Vector $FF0000 Description HI08 Bootstrap in 68302 bus In mode F: boot from HI08 in 68302/68360 Bus mode, the bootstrap program sets the host interface to interface with the Motorola 68302 or 68360 bus. If the host processor sets host flag 0 (HF0) in the HCR while writing the initialization program, the bootstrap program stops loading instructions, jumps to the starting address specified, and executes the loaded program. 4.4 INTERRUPT SOURCES AND PRIORITIES DSP56309 interrupt handling, like that of all DSP56300 family members, has been optimized for DSP applications. Refer to Section 7 of the DSP56300 Family Manual. The interrupt table is located in the 256 locations of program memory to which the vector base address (VBA) register in the program control unit (PCU) points. 4.4.1 Interrupt Sources Each interrupt is allocated two instructions in the table, so there are 128 table entries for interrupt handling. Table 4-2 shows the table entry address for each interrupt source. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 4-9 Freescale Semiconductor, Inc. Core Configuration Interrupt Sources and Priorities The DSP56309 initialization program loads the table entry for each interrupt serviced with two interrupt servicing instructions. In the DSP56309, only 46 of the 128 vector addresses are used for specific interrupt sources. The remaining 82 are reserved. If you know that certain interrupts will not be used, those interrupt vector locations can be used for program or data storage. Table 4-2 Interrupt Sources Interrupt Starting Address VBA:$00 VBA:$02 VBA:$04 VBA:$06 VBA:$08 VBA:$0A VBA:$0C VBA:$0E VBA:$10 VBA:$12 VBA:$14 VBA:$16 VBA:$18 VBA:$1A VBA:$1C VBA:$1E VBA:$20 VBA:$22 VBA:$24 VBA:$26 VBA:$28 VBA:$2A VBA:$2C VBA:$2E Interrupt Priority Level Range 3 3 3 3 3 3 3 3 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 Hardware RESET Stack Error Illegal Instruction Debug Request Interrupt Trap Non-Maskable Interrupt (NMI) Reserved Reserved IRQA IRQB IRQC IRQD DMA Channel 0 DMA Channel 1 DMA Channel 2 DMA Channel 3 DMA Channel 4 DMA Channel 5 TIMER 0 Compare TIMER 0 Overflow TIMER 1 Compare TIMER 1 Overflow TIMER 2 Compare TIMER 2 Overflow Freescale Semiconductor, Inc... Interrupt Source 4-10 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Core Configuration Interrupt Sources and Priorities Table 4-2 Interrupt Sources (Continued) Interrupt Starting Address VBA:$30 VBA:$32 VBA:$34 VBA:$36 VBA:$38 VBA:$3A VBA:$3C VBA:$3E VBA:$40 VBA:$42 VBA:$44 VBA:$46 VBA:$48 VBA:$4A VBA:$4C VBA:$4E VBA:$50 VBA:$52 VBA:$54 VBA:$56 VBA:$58 VBA:$5A VBA:$5C VBA:$5E VBA:$60 VBA:$62 VBA:$64 VBA:$66 : VBA:$FE Interrupt Priority Level Range 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 : 02 ESSI0 Receive Data ESSI0 Receive Data With Exception Status ESSI0 Receive Last Slot ESSI0 Transmit Data ESSI0 Transmit Data With Exception Status ESSI0 Transmit Last Slot Reserved Reserved ESSI1 Receive Data ESSI1 Receive Data With Exception Status ESSI1 Receive Last Slot ESSI1 Transmit Data ESSI1 Transmit Data With Exception Status ESSI1 Transmit Last Slot Reserved Reserved SCI Receive Data SCI Receive Data With Exception Status SCI Transmit Data SCI Idle Line SCI Timer Reserved Reserved Reserved Host Receive Data Full Host Transmit Data Empty Host Command (Default) Reserved : Reserved Interrupt Source Freescale Semiconductor, Inc... MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 4-11 Freescale Semiconductor, Inc. Core Configuration Interrupt Sources and Priorities 4.4.2 Interrupt Priority Levels The DSP56309 has a four-level interrupt priority structure. Each interrupt has two interrupt priority level bits (IPL[1:0]) that determine its interrupt priority level. Level 0 is the lowest priority; Level 3 is the highest-level priority and is non-maskable. Table 4-3 defines the IPL bits. Table 4-3 Interrupt Priority Level Bits IPL bits Interrupts Enabled No Yes Yes Yes Interrupts Masked N 0 0, 1 0, 1, 2 Interrupt Priority Level 0 1 2 3 Freescale Semiconductor, Inc... xxL1 0 0 1 1 xxL0 0 1 0 1 4-12 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Core Configuration Interrupt Sources and Priorities There are two interrupt priority registers in the DSP56309. The IPRC is dedicated to DSP56300 core interrupt sources, and IPRP is dedicated to DSP56309 peripheral interrupt sources. IPRC is shown in Figure 4-1 and IPRP is shown in Figure 4-2. 11 IDL2 10 IDL1 9 IDL0 8 ICL2 7 ICL1 6 ICL0 5 IBL2 4 IBL1 3 IBL0 2 IAL2 1 IAL1 0 IAL0 IRQA IPL IRQA mode IRQB IPL IRQB mode IRQC IPL IRQC mode IRQD IPL IRQD mode Freescale Semiconductor, Inc... 23 D5L1 22 D5L0 21 D4L1 20 D4L0 19 D3L1 18 D3L0 17 D2L1 16 15 14 D1L0 13 D0L1 12 D0L0 DMA0 IPL DMA1 IPL DMA2 IPL DMA3 IPL DMA4 IPL DMA5 IPL D2L0 D1L1 Figure 4-1 Interrupt Priority Register C (IPR-C) (X:$FFFFFF) 11 10 9 T0L1 8 T0L0 7 6 5 4 S1L0 3 S0L1 2 S0L0 1 0 SCL1 SCL0 S1L1 HPL1 HPL0 HI08 IPL ESSI0 IPL ESSI1 IPL SCI IPL TRIPLE TIMER IPL reserved 23 22 21 20 19 18 17 16 15 14 13 12 reserved Figure 4-2 Interrupt Priority Register P (IPR-P) (X:$FFFFFE) MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 4-13 Freescale Semiconductor, Inc. Core Configuration Interrupt Sources and Priorities 4.4.3 Interrupt Source Priorities Within an IPL If more than one interrupt request is pending when an instruction executes, the interrupt source with the highest IPL is serviced first. When several interrupt requests having the same IPL are pending, another fixed-priority structure within that IPL determines which interrupt source is serviced first. This fixed priority list of interrupt sources within an IPL is shown in Table 4-4. Table 4-4 Interrupt Source Priorities within an IPL Freescale Semiconductor, Inc... Priority Interrupt Source Level 3 (Nonmaskable) Highest N N N N Lowest Hardware RESET Stack Error Illegal Instruction Debug Request Interrupt Trap Non-Maskable Interrupt Levels 0, 1, 2 (Maskable) Highest N N N N N N N N N IRQA (External Interrupt) IRQB (External Interrupt) IRQC (External Interrupt) IRQD (External Interrupt) DMA Channel 0 Interrupt DMA Channel 1 Interrupt DMA Channel 2 Interrupt DMA Channel 3 Interrupt DMA Channel 4 Interrupt DMA Channel 5 Interrupt 4-14 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Core Configuration Interrupt Sources and Priorities Table 4-4 Interrupt Source Priorities within an IPL (Continued) Priority N N N N Interrupt Source Host Command Interrupt Host Transmit Data Empty Host Receive Data Full ESSI0 RX Data with Exception Interrupt ESSI0 RX Data Interrupt ESSI0 Receive Last Slot Interrupt ESSI0 TX Data With Exception Interrupt ESSI0 Transmit Last Slot Interrupt ESSI0 TX Data Interrupt ESSI1 RX Data With Exception Interrupt ESSI1 RX Data Interrupt ESSI1 Receive Last Slot Interrupt ESSI1 TX Data With Exception Interrupt ESSI1 Transmit Last Slot Interrupt ESSI1 TX Data Interrupt SCI Receive Data With Exception Interrupt SCI Receive Data SCI Transmit Data SCI Idle Line SCI Timer TIMER0 Overflow Interrupt TIMER0 Compare Interrupt TIMER1 Overflow Interrupt TIMER1 Compare Interrupt Freescale Semiconductor, Inc... N N N N N N N N N N N N N N N N N N N N MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 4-15 Freescale Semiconductor, Inc. Core Configuration DMA Request Sources Table 4-4 Interrupt Source Priorities within an IPL (Continued) Priority N Lowest Interrupt Source TIMER2 Overflow Interrupt TIMER2 Compare Interrupt 4.5 DMA REQUEST SOURCES Freescale Semiconductor, Inc... The DMA request source bits (DRS[4:0]) in the DMA control/status registers) encode the source of DMA requests used to trigger DMA transfers. The DMA request sources can be internal peripherals or external devices requesting service through the IRQA, IRQB, IRQC, or IRQD signals. Table 4-5 describes the meanings of the DRS bits. Table 4-5 DMA Request Sources DMA Request Source Bits DRS4... DRS0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 Requesting Device External (IRQA signal) External (IRQB signal) External (IRQC signal) External (IRQD signal) Transfer done from DMA channel 0 Transfer done from DMA channel 1 Transfer done from DMA channel 2 Transfer done from DMA channel 3 Transfer done from DMA channel 4 Transfer done from DMA channel 5 ESSI0 Receive Data (RDF0 = 1) ESSI0 Transmit Data (TDE0 = 1) ESSI1 Receive Data (RDF1 = 1) 4-16 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Core Configuration Operating Mode Register (OMR) Table 4-5 DMA Request Sources (Continued) DMA Request Source Bits DRS4... DRS0 01101 01110 01111 10000 Requesting Device ESSI1 Transmit Data (TDE1 = 1) SCI Receive Data (RDRF = 1) SCI Transmit Data (TDRE = 1) Timer0 (TCF0 = 1) Timer1 (TCF1 = 1) Timer2 (TCF2 = 1) Host Receive Data Full (HRDF = 1) Host Transmit Data Empty (HTDE = 1) Reserved Freescale Semiconductor, Inc... 10001 10010 10011 10100 1010111111 4.6 OPERATING MODE REGISTER (OMR) The OMR is a 24-bit, read/write register divided into three byte-sized units. The first two bytes (COM and EOM) control the chipOs operating mode. The third byte (SCS) controls and monitors the stack extension. The OMR control bits are shown in Figure 4-3. Refer to the DSP56300 Family Manual for a complete description of the OMR. SCS EOM COM 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PEN SEN WRP EOV EUN XYS ATE APD ABE BRT TAS BE CDP1:0 MS SD EBD MD MC MB MA PENNPatch Enable ATENAddress Tracing Enable MSNMemory Switch Mode SENNStack Extension Enable APDNAddress Priority Disable SDNStop Delay WRPNExtended Stack Wrap Flag ABENAsynch. Bus Arbitration Enable EBDNExternal Bus Disable EOVNExtended Stack Overflow Flag BRTNBus Release Timing MDNOperating Mode D EUNNExtended Stack Underflow Flag TASNTA Synchronize Select MCNOperating Mode C XYSNStack Extension Space Select BENBurst Mode Enable MBNOperating Mode B CDP1NCore-DMA Priority 1 MANOperating Mode A CDP0NCore-DMA Priority 0 - Reserved bit. Read as zero, should be written with zero for future compatibility. Figure 4-3 DSP56309 Operating Mode Register (OMR) MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 4-17 Freescale Semiconductor, Inc. Core Configuration PLL Control Register 4.7 PLL CONTROL REGISTER The PLL Control (PCTL) register is an X-I/O mapped, 24-bit, read/write register that directs the operation of the on-chip PLL. The PCTL control bits are shown in Figure 4-4. Refer to the DSP56300 Family Manual for a full description of the PCTL. 11 MF11 23 PD3 10 MF10 22 PD2 9 MF9 21 PD1 8 MF8 20 PD0 7 MF7 19 COD 6 MF6 18 PEN 5 MF5 17 PSTP 4 MF4 16 XTLD 3 MF3 15 XTLR 2 MF2 14 DF2 1 MF1 13 DF1 0 MF0 12 DF0 AA0852 Freescale Semiconductor, Inc... Figure 4-4 PLL Control (PCTL) Register 4.7.1 PCTL PLL Multiplication Factor Bits 011 The multiplication factor bits (MF[11:0]) define the Multiplication Factor (MF) that is applied to the PLL input frequency. The MF bits are cleared during a DSP56309 hardware reset, which corresponds to an MF of one. 4.7.2 PCTL XTAL Disable Bit (XTLD) Bit 16 The XTAL disable bit (XTLD) controls the on-chip crystal oscillator XTAL output. The XTLD bit is cleared during a DSP56309 hardware reset, which means that the XTAL output signal is active, permitting normal operation of the crystal oscillator. 4.7.3 PCTL Predivider Factor Bits (PD0PD3) Bits 2023 The predivider factor bits (PD0PD3) define the predivision factor (PDF) to be applied to the PLL input frequency. The PD0PD3 bits are cleared during a DSP56309 hardware reset, which corresponds to a PDF of one. 4.8 DEVICE IDENTIFICATION REGISTER (IDR) The device identification register (IDR) is a 24-bit, read-only factory programmed register that identifies DSP56300 family members. It specifies the derivative number and 4-18 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Core Configuration AA Control Registers (AAR0AAR3) revision number of the device. This information can be used in testing or by software. shows the contents of the IDR. Revision numbers are assigned as follows: $0 is revision 0, $1 is revision A, and so on. Because the DSP56309 is based on the DSP56302, its identification number is based on the derivative number and revision number of that device. 23 16 15 12 11 Derivative Number 0 Freescale Semiconductor, Inc... Reserved Revision Number $00 $2 $302 Figure 4-5 Identification Register Configuration (Revision 0) 4.9 AA CONTROL REGISTERS (AAR0AAR3) The address attribute register (AAR) appears in Figure 4-6. There are four of these registers in the DSP56309 (AAR0AAR3), one for each AA signal. For a full description of the address attribute registers see the DSP56300 Family Manual. Address multiplexing is not supported by the DSP56309. Bit 6 (BAM) of the AARs is reserved and should have only 0 written to it. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 4-19 Freescale Semiconductor, Inc. Core Configuration JTAG Boundary Scan Register (BSR) 11 10 9 8 7 6 5 4 3 2 1 0 BNC3 BNC2 BNC1 BNC0 BPAC BYEN BXEN BPEN BAAP BAT1 BAT0 Freescale Semiconductor, Inc... External access type AA pin polarity Program space enable X data space enable Y data space enable Reserved Packing enable Number of address bit to compare 23 22 21 20 19 18 17 16 15 14 13 12 BAC11 BAC10 BAC9 BAC8 BAC7 BAC6 BAC5 BAC4 BAC3 BAC2 BAC1 BAC0 Address to compare - Reserved Bit Figure 4-6 Address Attribute Registers (AAR0AAR3) (X:$FFFFF9$FFFFF6) 4.10 JTAG BOUNDARY SCAN REGISTER (BSR) The BSR in the DSP56309 JTAG implementation contains bits for all device signal and clock pins and associated control signals. All DSP56309 bidirectional pins have a corresponding register bit in the BSR for pin data and are controlled by an associated control bit in the BSR. The BSR is documented in Section 11.5NDSP56309 Boundary Scan Register on page 11-13. The JTAG code is listed in Appendix CNDSP56309 BSDL Listing. 4-20 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. SECTION 5 GENERAL-PURPOSE I/O Freescale Semiconductor, Inc... MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 5-1 Freescale Semiconductor, Inc. General-Purpose I/O 5.1 5.2 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Freescale Semiconductor, Inc... 5-2 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. General-Purpose I/O Introduction 5.1 INTRODUCTION The DSP56309 provides thirty-four bidirectional signals that can be configured as GPIO signals or as dedicated peripheral signals. No dedicated GPIO signals are provided. All of these signals are GPIO by default after reset. The control register settings of the DSP56309Os peripherals determine whether these signals function as GPIO or as dedicated peripheral signals. This section describes how signals can function as GPIO. 5.2 PROGRAMMING MODEL Freescale Semiconductor, Inc... Section 2NSignal/Connection Descriptions of this manual documents the special uses of these signals in detail. There are five groups of these signals. They can be controlled separately or as groups. The groups include the following signals: Port B: sixteen GPIO signals (shared with the HI08 signals) Port C: six GPIO signals (shared with the ESSI0 signals) Port D: six GPIO signals (shared with the ESSI1 signals) Port E: three GPIO signals (shared with the SCI signals) Timers: three GPIO signals (shared with the Triple Timer signals) 5.2.1 Port B Signals and Registers Each of the 16 Port B signals not used as a HI08 signal can be configured as a GPIO signal. The GPIO functionality of Port B is controlled by three registers: host control register (HCR), host port GPIO data register (HDR), and host port GPIO direction register (HDDR). These registers are documented in Section 6NHost Interface (HI08) of this manual. 5.2.2 Port C Signals and Registers Each of the six Port C signals not used as an ESSI0 signal can be configured as a GPIO signal. The GPIO functionality of Port C is controlled by three registers: Port C control register (PCRC), Port C direction register (PRRC), and Port C data register (PDRC). These registers are documented in Section 7NEnhanced Synchronous Serial Interface (ESSI) of this manual. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 5-3 Freescale Semiconductor, Inc. General-Purpose I/O Programming Model 5.2.3 Port D Signals and Registers Each of the six Port D signals not used as a ESSI1 signal can be configured as a GPIO signal. The GPIO functionality of Port D is controlled by three registers: Port D control register (PCRD), Port D direction register (PRRD) and Port D data register (PDRD). These registers are also documented in Section 7NEnhanced Synchronous Serial Interface (ESSI) of this manual. 5.2.4 Port E Signals and Registers Freescale Semiconductor, Inc... Each of the three Port E signals not used as a SCI signal can be configured as a GPIO signal. The GPIO functionality of Port E is controlled by three registers: Port E control register (PCRE), Port E direction register (PRRE) and Port E data register (PDRE). These registers are documented in Section 8NSerial Communication Interface (SCI) of this manual. 5.2.5 Triple Timer Signals Each of the three triple timer interface signals (TIO0TIO2) not used as a timer signal can be configured as a GPIO signal. Each signal is controlled by the appropriate timer control status register (TCSR0TCSR2). These registers are documented in Section 9NTriple Timer Module of this manual. 5-4 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. SECTION 6 HOST INTERFACE (HI08) Freescale Semiconductor, Inc... MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 6-1 Freescale Semiconductor, Inc. Host Interface (HI08) 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 HI08 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 HI08 HOST PORT SIGNALS. . . . . . . . . . . . . . . . . . . . . . . . . 6-6 HI08 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 HI08 DSP SIDE PROGRAMMEROS MODEL. . . . . . . . . . . . . 6-8 HI08-EXTERNAL HOST PROGRAMMEROS MODEL . . . . . 6-20 SERVICING THE HOST INTERFACE . . . . . . . . . . . . . . . . 6-31 HI08 PROGRAMMING MODEL QUICK REFERENCE. . . . 6-34 Freescale Semiconductor, Inc... 6-2 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Host Interface (HI08) Introduction 6.1 INTRODUCTION The Host Interface (HI08) is a byte-wide, full-duplex, double-buffered parallel port that can connect directly to the data bus of a host processor. The HI08 supports a variety of buses and provides glueless connection with a number of industry-standard microcomputers, microprocessors, and DSPs. The host bus can operate asynchronously to the DSP core clock, so the HI08 registers are divided into two banks. The host register bank is accessible to the external host and the DSP register bank is accessible to the DSP core. Freescale Semiconductor, Inc... The HI08 supports two classes of interfaces: Host Processor/Microcontroller (MCU) connection interface GPIO port Signals not used as HI08 port signals can be configured as GPIO signals, up to a total of 16. 6.2 HI08 FEATURES This section lists the features of the host-to-DSP and DSP-to-host interfaces. Further details are given in Section 6.5NHI08 DSP Side ProgrammerOs Model and Section 6.8NHI08 Programming Model Quick Reference. Also, see Table 6-13 on page 6-34. 6.2.1 Host to DSP Core Interface Mapping: Registers are directly mapped into eight internal X data memory locations DSP56309 24-bit (native) data words are supported, as are 8-bit and 16-bit words DSP-to-host Host-to-DSP Data word: Transfer modes: MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 6-3 Freescale Semiconductor, Inc. Host Interface (HI08) HI08 Features Host command Software polled Interrupt driven Core DMA accesses Memory-mapped registers allow the standard MOVE instruction to be used to transfer data between the DSP56309 and external hosts. Special MOVEP instruction provides for I/O service capability using fast interrupts. Bit addressing instructions (e.g., BCHG, BCLR, BSET, BTST, JCLR, JSCLR, JSET, JSSET) simplify I/O service routines. Handshaking protocols: Instructions: Freescale Semiconductor, Inc... 6.2.2 HI08-to-Host Processor Interface Sixteen signals support non-multiplexed or multiplexed buses: H0H7/HAD0HAD7 host data bus (H0H7) or host multiplexed address/data bus (HAD0HAD7) HAS/HA0 address strobe (HAS) or host address line (HA0) HA8/HA1 host address line (HA8) or host address line (HA1) HA9/HA2 host address line (HA9) or host address line (HA2) HRW/HRD read/write select (HRW) or read strobe (HRD) HDS/HWR data strobe (HDS) or write strobe (HWR) HCS/HA10 host chip select (HCS) or host address line (HA10) HREQ/HTRQ host request (HREQ) or host transmit request (HTRQ) HACK/HRRQ host acknowledge (HACK) or host receive request (HRRQ) HI08 registers are mapped into eight consecutive locations in external bus address space. The HI08 acts as a memory or I/O-mapped peripheral for microprocessors, microcontrollers, etc. Mapping: 6-4 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Host Interface (HI08) HI08 Features Data word: 8-bit Transfer modes: Mixed 8-bit, 16-bit, and 24-bit data transfers DSP-to-host Host-to-DSP Host command Software polled Interrupt-driven (Interrupts are compatible with most processors, including the MC68000, 8051, HC11, and Hitachi H8.) Separate interrupt lines for each interrupt source Special host commands force DSP core interrupts under host processor control. These commands are useful for these purposes: Real-time production diagnostics Creating a debugging window for program development Host control protocols Interface capabilities: Glueless interface (no external logic required) to these devices: Motorola HC11 Hitachi H8 8051 family Thomson P6 family Minimal glue-logic (pullups, pulldowns) required to interface these devices: ISA bus Motorola 68K family IntelO X86 family Handshaking protocols: Freescale Semiconductor, Inc... Dedicated interrupts: MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 6-5 Freescale Semiconductor, Inc. Host Interface (HI08) HI08 Host Port Signals 6.3 HI08 HOST PORT SIGNALS The host port signals are documented in Section 2.8NHost Interface (HI08). Each host port signal can be programmed as a host port signal or as a GPIO signal, PB0PB15, as in Table 6-1 through Table 6-3. Table 6-1 HI08 Signal Definitions for Various Operational Modes HI08 Port Signal Multiplexed Address/Data Bus Mode HAD0HAD7 HAS/HAS HA8 HA9 HA10 Non-Multiplexed Bus Mode H0H7 HA0 HA1 HA2 HCS/HCS GPIO Mode PB0PB7 PB8 PB9 PB10 PB13 Freescale Semiconductor, Inc... HAD0HAD7 HAS/HA0 HA8/HA1 HA9/HA2 HCS/HA10 Table 6-2 HI08 Data Strobe Signals HI08 Port Signal HRW/HRD HDS/HWR Single Strobe Bus HRW HDS/HDS Dual Strobe Bus HRD/HRD HWR/HWR GPIO Mode PB11 PB12 Table 6-3 HI08 Host Request Signals HI08 Port Signal HREQ/ HTRQ HACK/ HRRQ Vector Required HREQ/HREQ HACK/HACK No Vector Required HTRQ/HTRQ HRRQ/HRRQ GPIO Mode PB14 PB15 6-6 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Host Interface (HI08) HI08 Block Diagram 6.4 HI08 BLOCK DIAGRAM Figure 6-1 shows the HI08 registers. The top row of registers are for access by the DSP core. The bottom row of registers are for access by the host processor. HCR = Host Control Register HSR = Host Status Register HPCR = Host Port Control Register HBAR = Host Base Address register HTX = Host Transmit register HRX = Host Receive register HDDR = Host Data Direction Register HDR = Host Data Register Core DMA Data Bus Freescale Semiconductor, Inc... DSP Peripheral Data Bus 24 HCR 24 HSR 24 HDDR 24 HDR 24 HBAR 8 24 HPCR 24 HTX 24 24 HRX 24 Address Comparator 24 24 5 3 ISR ICR CVR IVR Latch RXH RXM RXL TXH TXM TXL 8 8 8 8 8 3 8 8 8 8 8 8 HOST Bus ICR = Interface Control Register CVR = Command Vector Register ISR = Interface Status Register IVR = Interrupt Vector Register RXH = Receive Register High RXM = Receive Register Middle RXL = Receive Register Low TXH = Transmit Register High TXM = Transmit Register Middle TXL = Transmit Register High AA0657 Figure 6-1 HI08 Block Diagram MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 6-7 Freescale Semiconductor, Inc. Host Interface (HI08) HI08 DSP Side ProgrammerOs Model 6.5 HI08 DSP SIDE PROGRAMMEROS MODEL Freescale Semiconductor, Inc... The DSP56309 core treats the HI08 as a memory-mapped peripheral occupying eight 24-bit words in X data memory space. The DSP treats the HI08 as a normal memory-mapped peripheral, employing either standard polled or interrupt-driven programming techniques. Separate transmit and receive data registers are double-buffered to allow the DSP and host processor to transfer data efficiently at high speed. Direct memory mapping allows the DSP56309 core to communicate with the HI08 registers using standard instructions and addressing modes. In addition, the MOVEP instruction allows direct data transfers between DSP56309 internal memory and the HI08 registers or vice versa. There are two kinds of host processor registers, data and control, with eight registers in all. All eight registers can be accessed by the DSP core but not by the external host. Data registers are 24-bit registers used for high-speed data transfer to and from the DSP. Host data receive register (HRX) Host data transmit register (HTX) The DSP side control registers are 16-bit registers that control DSP functions. The eight MSBs in the DSP side control registers are read by the DSP56309 as 0. Those registers are as follows: Host control register (HCR) Host status register (HSR) Host base address register (HBAR) Host port control register (HPCR) Host GPIO data direction register (HDDR) Host GPIO data register (HDR) Both hardware RESET signals and software RESET instructions disable the HI08. After reset, the HI08 signals are configured to GPIO and disconnected from the DSP56309 core (i.e., the signals are left floating). 6.5.1 Host Receive Data Register (HRX) The HRX register handles host-to-DSP data transfers. The DSP56309 views it as a 24-bit read-only register. Its address is X:$FFFFC6. It is loaded with 24-bit data from the 6-8 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Host Interface (HI08) HI08 DSP Side ProgrammerOs Model transmit data registers (TXH:TXM:TXL on the host side) when both the hostOs transmit data register empty (ISR:TXDE) bit and the DSPOs host receive data full (HSR:HRDF) bits are cleared. The transfer operation sets both the TXDE and HRDF bits. When the HRDF bit is set, the HRX register contains valid data. The DSP56309 sets the HRIE bit (HCR, bit 0) to cause a host receive data interrupt when HRDF is set. When the DSP56309 reads the HRX register, the HRDF bit is cleared. 6.5.2 Host Transmit Data Register (HTX) Freescale Semiconductor, Inc... The HTX register handles for DSP-to-host data transfers. The DSP56309 views it as a 24-bit write-only register. Its address is X:$FFFFC7. Writing to the HTX register clears the DSPOs host transfer data empty (HSR:HTDE) bit. The contents of the HTX register are transferred as 24-bit data to the receive byte registers (RXH:RXM:RXL) when both the HTDE and the hostOs receive data full (ISR:RXDF) bits are cleared. This transfer operation sets the HTDE and RXDF bits. The DSP56309 sets the HTIE bit to cause a host transmit data interrupt when HTDE is set. To prevent the previous data from being overwritten, data should not be written to the HTX until the HTDE bit is set. Note: During data writes to a peripheral device, there is a two-cycle pipeline delay until any status bits affected by this operation are updated. If you read any of those status bits within the next two cycles, the bit does not reflect its current status. See the DSP56300 Family Manual, Appendix B, Polling a Peripheral Device for Write for further details. 6.5.3 Host Control Register (HCR) The HCR is a 16-bit, read/write control register by which the DSP core controls the HI08 operating mode. Initialization values for HCR bits are documented in Section 6.5.9NDSP Side Registers After Reset. Reserved bits are read as 0 and should be written with 0 for future compatibility. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HF3 HF2 HCIE HTIE HRIE NReserved bit, read as 0, should be written with 0 for future compatibility. AA0658 Figure 6-2 Host Control Register (HCR) (X:$FFFFC2) MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 6-9 Freescale Semiconductor, Inc. Host Interface (HI08) HI08 DSP Side ProgrammerOs Model 6.5.3.1 HCR Host Receive Interrupt Enable (HRIE) Bit 0 The HRIE bit generates a host receive data interrupt request if the host receive data full (HRDF) bit in the host status register (HSR, Bit 0), is set. The HRDF bit is set when data is written to the HRX. If HRIE is cleared, HRDF interrupts are disabled. 6.5.3.2 HCR Host Transmit Interrupt Enable (HTIE) Bit 1 The HTIE bit generates a host transmit data interrupt request if the host transmit data empty (HTDE) bit in the HSR is set. The HTDE bit is set when data is read from the HTX. If HTIE is cleared, HTDE interrupts are disabled. Freescale Semiconductor, Inc... 6.5.3.3 HCR Host Command Interrupt Enable (HCIE) Bit 2 The HCIE bit generates a host command interrupt request if the host command pending (HCP) status bit in the HSR is set. If HCIE is cleared, HCP interrupts are disabled. The interrupt address is determined by the host command vector register (CVR). Note: If more than one interrupt request source is asserted and enabled (e.g., HRDF is set, HCP is set, HRIE is set, and HCIE is set), the HI08 generates interrupt requests according to priorities shown in Table 6-4. Table 6-4 Host Command Interrupt Priority List Priority Highest Interrupt Source Host Command (HCP = 1) Transmit Data (HTDE = 1) Lowest Receive Data (HRDF = 1) 6.5.3.4 HCR Host Flags 2,3 (HF[3:2]) Bits 3, 4 HF[3:2] bits are general-purpose flags for DSP-to-host communication. The DSP core sets and clears them. The values of HF[3:2] are reflected in the interface status register (ISR); that is, if they are modified by the DSP software, the host processor can read the modified values by reading the ISR. These two flags can be used individually or as encoded pairs in a simple DSP-to-host communication protocol, implemented in both the DSP and the host processor software. 6.5.3.5 HCR Reserved Bits 5-15 These bits are reserved. They are read as 0 and should be written with 0. 6-10 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Host Interface (HI08) HI08 DSP Side ProgrammerOs Model 6.5.4 Host Status Register (HSR) The HSR is a 16-bit, read-only status register by which the DSP reads the HI08 status and flags. The host processor cannot access it directly. Reserved bits are read as 0 and should be written with 0. The initialization values for the HSR bits are described in Section 6.5.9NDSP Side Registers After Reset on page 6-18. 15 14 13 12 11 10 9 8 7 6 5 4 HF1 3 HF0 2 HCP 1 0 HTDE HRDF Freescale Semiconductor, Inc... NReserved bit, read as 0, should be written with 0 for future compatibility. AA0659 Figure 6-3 Host Status Register (HSR) (X:$FFFFC3) 6.5.4.1 HSR Host Receive Data Full (HRDF) Bit 0 The HRDF bit indicates that the host receive data register (HRX) contains data from the host processor. HRDF is set when data is transferred from the TXH:TXM:TXL registers to the HRX register. If HRDF is set, the HI08 generates a receive data full DMA request. HRDF is cleared when the DSP core reads the HRX. HRDF is also cleared when the host processor uses the initialize function. 6.5.4.2 HSR Host Transmit Data Empty (HTDE) Bit 1 The HTDE bit indicates that the host transmit data register (HTX) is empty and can be written by the DSP core. HTDE is set when the HTX register is transferred to the RXH:RXM:RXL registers. HTDE is also set when the host processor uses the initialize function. If HTDE is set, the HI08 generates a transmit data full DMA request. HTDE is cleared when HTX is written by the DSP core. 6.5.4.3 HSR Host Command Pending (HCP) Bit 2 The HCP bit indicates that the host has set the HC bit and that a host command interrupt is pending. The HCP bit reflects the status of the HC bit in the CVR. HC and HCP are cleared by the HI08 hardware when the interrupt request is serviced by the DSP core. If the host clears HC, HCP is also cleared. 6.5.4.4 HSR Host Flags 0, 1 (HF[1:0]) Bits 3, 4 HF[1:0] bits are used as general-purpose flags for host-to-DSP communication. HF[1:0] can be set or cleared by the host. These bits reflect the status of host flags HF[1:0] in the ICR on the host side. They can be used individually or as encoded pairs in a simple host-to-DSP communication protocol implemented in both the DSP and the host processor software. 6.5.4.5 HSR Reserved Bits 5-15 These bits are reserved. They are read as 0 and should be written with 0. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 6-11 Freescale Semiconductor, Inc. Host Interface (HI08) HI08 DSP Side ProgrammerOs Model 6.5.5 Host Base Address Register (HBAR) The HBAR is used in multiplexed bus modes. This register, illustrated in Figure 6-4, selects the base address where the host side registers are mapped into the bus address space. The address from the host bus is compared with the base address as programmed in the base address register. If the addresses match, an internal chip select is generated. The use of this register by the chip select logic is described in Figure 6-5. 15 14 13 12 11 10 9 8 7 BA10 6 BA9 5 BA8 4 BA7 3 BA6 2 BA5 1 BA4 0 BA3 AA0665 Freescale Semiconductor, Inc... Figure 6-4 Host Base Address Register (HBAR) (X:$FFFFC5) 6.5.5.1 HBAR Base Address (BA[10:3]) Bits 0-7 These bits reflect the base address where the host-side registers are mapped into the bus address space. 6.5.5.2 HBAR Reserved Bits 8-15 These bits are reserved. They are read as 0 and should be written with 0. HAD[07] Latch HAS HA[8:10] Base Address Register A[3:7] Comparator Chip select DSP Peripheral Data Bus 8 bits AA0666 Figure 6-5 Self Chip Select Logic 6.5.6 Host Port Control Register (HPCR) The HPCR is a 16-bit, read/write control register by which the DSP controls the HI08 operating mode. Reserved bits are read as 0 and should be written with 0 for future compatibility. The initialization values for the HPCR bits are described in Section 6.5.9NDSP Side Registers After Reset. The HPCR bits are illustrated in Figure 6-6. 6-12 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Host Interface (HI08) HI08 DSP Side ProgrammerOs Model 15 HAP 14 HRP 13 12 11 10 9 8 7 6 HEN 5 4 3 2 1 0 HCSP HDDS HMUX HASP HDSP HROD HAEN HREN HCSEN HA9EN HA8EN HGEN NReserved bit, read as 0, should be written with 0 for future compatibility. AA0660 Figure 6-6 Host Port Control Register (HPCR) (X:$FFFFC4) Note: To assure proper operation of the DSP56309, the HPCR bits HAP, HRP, HCSP, HDDS, HMUX, HASP, HDSP, HROD, HAEN, and HREN should be changed only if HEN is cleared. To assure proper operation of the DSP56309, the HPCR bits HAP, HRP, HCSP, HDDS, HMUX, HASP, HDSP, HROD, HAEN, HREN, HCSEN, HA9EN, and HA8EN should not be set when HEN is set or simultaneously with setting HEN. 6.5.6.1 HPCR Host GPIO Port Enable (HGEN) Bit 0 If HGEN is set, signals configured as GPIO are enabled. If this bit is cleared, signals configured as GPIO are disconnected; outputs are high impedance, and inputs are electrically disconnected. Signals configured as HI08 are not affected by the value of HGEN. 6.5.6.2 HPCR Host Address Line 8 Enable (HA8EN) Bit 1 If HA8EN is set and the HI08 is in multiplexed bus mode, then HA8/A1 acts as host address line 8 (HA8). If this bit is cleared and the HI08 is in multiplexed bus mode, then HA8/HA1 acts as a GPIO signal according to the value of the HDDR and HDR. Note: HA8EN is ignored when the HI08 is not in the multiplexed bus mode (HMUX is cleared). Freescale Semiconductor, Inc... 6.5.6.3 HPCR Host Address Line 9 Enable (HA9EN) Bit 2 If HA9EN is set and the HI08 is in multiplexed bus mode, then HA9/HA2 acts as host address line 9 (HA9). If this bit is cleared, and the HI08 is in multiplexed bus mode, then HA9/HA2 is configured as a GPIO signal according to the value of the HDDR and HDR. Note: HA9EN is ignored when the HI08 is not in the multiplexed bus mode (HMUX is cleared). 6.5.6.4 HPCR Host Chip Select Enable (HCSEN) Bit 3 If the HCSEN bit is set, then HCS/HA10 is used as host chip select (HCS) in the non-multiplexed bus mode (HMUX is cleared), and as host address line 10 (HA10) in the multiplexed bus mode (HMUX is set). If this bit is cleared, then HCS/HA10 is configured as a GPIO signal according to the value of the HDDR and HDR. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 6-13 Freescale Semiconductor, Inc. Host Interface (HI08) HI08 DSP Side ProgrammerOs Model 6.5.6.5 HPCR Host Request Enable (HREN) Bit 4 The HREN bit controls the host request signals. If HREN is set and the HI08 is in the single host request mode (HDRQ is cleared in the host interface control register (ICR)), HREQ/HTRQ is configured as the host request (HREQ) output. If HREN is cleared, HREQ/HTRQ and HACK/HRRQ are configured as GPIO signals according to the value of the HDDR and HDR. If HREN is set in the double host request mode (HDRQ is set in the ICR), HREQ/HTRQ is configured as the host transmit request (HTRQ) output and HACK/HRRQ as the host receive request (HRRQ) output. If HREN is cleared, HREQ/HTRQ and HACK/HRRQ are configured as GPIO signals according to the value of the HDDR and HDR. Freescale Semiconductor, Inc... 6.5.6.6 HPCR Host Acknowledge Enable (HAEN) Bit 5 The HAEN bit controls the HACK signal. In the single host request mode (HDRQ is cleared in the ICR), if HAEN and HREN are both set, HACK/HRRQ is configured as the host acknowledge (HACK) input. If HAEN or HREN is cleared, HACK/HRRQ is configured as a GPIO signal according to the value of the HDDR and HDR. In the double host request mode (HDRQ is set in the ICR), HAEN is ignored. 6.5.6.7 HPCR Host Enable (HEN) Bit 6 If HEN is set, the HI08 operates as the host interface. If HEN is cleared, the HI08 is not active, and all the HI08 signals are configured as GPIO signals according to the value of the HDDR and HDR. 6.5.6.8 HPCR Reserved Bit 7 This bit is reserved. It is read as 0 and should be written as 0. 6.5.6.9 HPCR Host Request Open Drain (HROD) Bit 8 The HROD bit controls the output drive of the host request signals. In the single host request mode (HDRQ is cleared in ICR), if HROD is cleared and host requests are enabled (HREN is set and HEN is set in HPCR), the HREQ signal is always driven by the HI08. If HROD is set and host requests are enabled, the HREQ signal is an open drain output. In the double host request mode (HDRQ is set in the ICR), if HROD is cleared and host requests are enabled (HREN is set and HEN is set in the HPCR), the HTRQ and HRRQ signals are always driven. If HROD is set and host requests are enabled, the HTRQ and HRRQ signals are open drain outputs. 6.5.6.10 HPCR Host Data Strobe Polarity (HDSP) Bit 9 If HDSP is cleared, the data strobe signals are configured as active low inputs, and data is transferred when the data strobe is low. If HDSP is set, the data strobe signals are configured as active high inputs, and data is transferred when the data strobe is high. The data strobe signals are either HDS by itself or both HRD and HWR together. 6-14 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Host Interface (HI08) HI08 DSP Side ProgrammerOs Model 6.5.6.11 HPCR Host Address Strobe Polarity (HASP) Bit 10 If HASP is cleared, the host address strobe (HAS) signal is an active low input, and the address on the host address/data bus is sampled when the HAS signal is low. If HASP is set, HAS is an active high address strobe input, and the address on the host address or data bus is sampled when the HAS signal is high. 6.5.6.12 HPCR Host Multiplexed Bus (HMUX) Bit 11 If HMUX is set, the HI08 latches the lower portion of a multiplexed address/data bus. In this mode the internal address line values of the host registers are taken from the internal latch. If HMUX is cleared, it indicates that the HI08 is connected to a non-multiplexed type of bus. The values of the address lines are then taken from the HI08 input signals. 6.5.6.13 HPCR Host Dual Data Strobe (HDDS) Bit 12 If the HDDS bit is cleared, the HI08 operates in the single-strobe bus mode. In this mode, the bus has a single data strobe signal for both reads and writes. If set, the HI08 operates in the dual-strobe bus mode. In this mode, the bus has two separate data strobes, one for data reads, the other for data writes. See Figure 6-7 and Figure 6-8 for more information on the two types of buses. . HRW Freescale Semiconductor, Inc... HDS In a single-strobe bus, a DS (data strobe) signal qualifies the access, while a R/W (Read-Write) signal specifies the direction of the access. AA0661 Figure 6-7 Single Strobe Bus MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 6-15 Freescale Semiconductor, Inc. Host Interface (HI08) HI08 DSP Side ProgrammerOs Model Data HWR Write Cycle Data Write Data In Read Data Out HRD Read Cycle Freescale Semiconductor, Inc... In dual strobe bus, there are separate HRD and HWR signals that specify the access as being a read or write access, respectively. AA0662 Figure 6-8 Dual Strobe Bus 6.5.6.14 HPCR Host Chip Select Polarity (HCSP) Bit 13 If the HCSP bit is cleared, the host chip select (HCS) signal is configured as an active low input and the HI08 is selected when the HCS signal is low. If the HCSP signal is set, HCS is configured as an active high input, and the HI08 is selected when the HCS signal is high. 6.5.6.15 HPCR Host Request Polarity (HRP) Bit 14 The HRP bit controls the polarity of the host request signals. In the single-host request mode (HDRQ is cleared in the ICR), if HRP is cleared, and host requests are enabled (HREN is set and HEN is set), the HREQ signal is an active low output. If HRP is set and host requests are enabled, the HREQ signal is an active high output. In the double-host request mode (HDRQ is set in the ICR), if HRP is cleared, and host requests are enabled (HREN is set and HEN is set), the HTRQ and HRRQ signals are active low outputs. If HRP is set, and host requests are enabled, the HTRQ and HRRQ signals are active high outputs. 6.5.6.16 HPCR Host Acknowledge Polarity (HAP) Bit 15 If the HAP bit is cleared, the host acknowledge (HACK) signal is configured as an active low input. The HI08 drives the contents of the IVR onto the host bus when the HACK signal is low. If the HAP bit is set, the HACK signal is configured as an active high input. The HI08 outputs the contents of the IVR when the HACK signal is high. 6-16 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Host Interface (HI08) HI08 DSP Side ProgrammerOs Model 6.5.7 Host Data Direction Register (HDDR) The HDDR controls the direction of the data flow for each of the HI08 signals configured as GPIO. It is illustrated in Figure 6-9. Even when the HI08 functions as the host interface, its unused signals can be configured as GPIO signals. For information on the HI08 GPIO configuration options, see Section 6.6.8NGeneral-Purpose I/O on page 6-30. If bit DRxx is set, the corresponding HI08 signal is configured as an output signal. If bit DRxx is cleared, the corresponding HI08 signal is configured as an input signal. 15 14 13 12 11 10 9 DR9 8 DR8 7 DR7 6 DR6 5 DR5 4 DR4 3 DR3 2 DR2 1 DR1 0 DR0 AA0663 Freescale Semiconductor, Inc... DR15 DR14 DR13 DR12 DR11 DR10 Figure 6-9 Host Data Direction Register (HDDR) (X:$FFFFC8) 6.5.8 Host Data Register (HDR) The HDR register holds the data value of the corresponding bits of the HI08 signals configured as GPIO signals. It is illustrated in Figure 6-10. The functionality of the Dxx bit depends on the corresponding HDDR bit (DRxx), as in Table 6-5. The HDR cannot be accessed by the host processor. 15 D15 14 D14 13 D13 12 D12 11 D11 10 D10 9 D9 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 AA0664 Figure 6-10 Host Data Register (HDR) (X:$FFFFC9) MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 6-17 Freescale Semiconductor, Inc. Host Interface (HI08) HI08 DSP Side ProgrammerOs Model Table 6-5 HDR and HDDR Functionality HDDR HDR Dxx DRxx Configured as GPIO signal 0 Read only bitN The value read is the binary value of the signal. The corresponding signal is configured as an input. Read/write bitN The value written is the value read. The corresponding signal is configured as an output, and is driven with the data written to Dxx. Configured as non-GPIO signal Read only bitNDoes not contain significant data. Freescale Semiconductor, Inc... 1 Read/write bitN The value written is the value read. 6.5.9 DSP Side Registers After Reset Table 6-6 shows the results of the four reset types on the bits in each of the HI08 registers accessible by the DSP56309. Reset types are as follows: Hardware reset (HW)Ncaused by the RESET signal Software reset (SW)Ncaused by executing the RESET instruction Individual reset (IR)Ncaused by clearing the HPCR:HEN Stop reset (ST)Ncaused by executing the STOP instruction. 6-18 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Host Interface (HI08) HI08 DSP Side ProgrammerOs Model Table 6-6 DSP Side Registers after Reset Reset Type Register Name HCR Register Data All bits HW Reset 0 SW Reset 0 IR Reset bit value indeterminate after reset N N 0 1 0 N N N empty empty ST Reset N Freescale Semiconductor, Inc... HPCR HSR All bits HF[1:0] HCP HTDE HRDF 0 0 0 1 0 $80 0 N empty empty 0 0 0 1 0 $80 0 N empty empty N N 0 1 0 N N N empty empty HBAR HDDR HDR HRX HTX BA[10:3] DR[15:0] D[15:0] HRX [23:0] HTX [23:0] 6.5.10 Host Interface DSP Core Interrupts The HI08 can request interrupt service from either the DSP56309 or the host processor. The DSP56309 interrupts are internal and do not require the use of an external interrupt signal. When the appropriate interrupt enable bit in the HCR is set, an interrupt condition caused by the host processor sets the appropriate bit in the HSR, generating an interrupt request to the DSP56309. (See Figure 6-11.) The DSP56309 acknowledges interrupts caused by the host processor by jumping to the appropriate interrupt service routine. There are three possible interrupts: Host command Transmit data register empty Receive data register full Although there is a set of vectors reserved for host command use, the host command can access any interrupt vector in the interrupt vector table. The DSP interrupt service MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 6-19 Freescale Semiconductor, Inc. Host Interface (HI08) HI08-External Host ProgrammerOs Model routine must read or write the appropriate HI08 register (e.g., clearing HRDF or HTDE) to clear the interrupt. For host command interrupts, the interrupt acknowledge from the DSP56309 program controller clears the pending interrupt condition. Enable 15 X:HCR HF3 HF2 HCIE HTIE HRIE 0 HCR DSP Core Interrupts Receive Data Full Freescale Semiconductor, Inc... Transmit Data Empty Host Command 15 X:HSR HF1 HF0 HCP 0 HTDE HRDF HSR Status AA0667 Figure 6-11 HSR-HCR Operation 6.6 HI08-EXTERNAL HOST PROGRAMMEROS MODEL The HI08 is a simple, high speed interface to a host processor. To the host bus, the HI08 appears to be eight byte-wide registers. Separate transmit and receive data registers are double-buffered to allow the DSP core and host processor to transfer data efficiently at high speed. The host can access the HI08 asynchronously by using polling techniques or interrupt-based techniques. The HI08 appears to the host processor as a memory-mapped peripheral occupying eight bytes in the host processor address space, as in Table 6-7 on page 6-22. The eight HI08 registers include the following: A control register (ICR) A status register (ISR) Three data registers (RXH/TXH, RXM/TXM, and RXL/TXL) Two vector registers (IVR and CVR) 6-20 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Host Interface (HI08) HI08-External Host ProgrammerOs Model The CVR is a special command register by which the host processor issues commands to the DSP56309. Only the host processor can access this register. Host processors can use standard host processor instructions (e.g., byte move) and addressing modes to communicate with the HI08 registers. The HI08 registers are aligned so that 8-bit host processors can use 8/16/24-bit load and store instructions for data transfers. The HREQ/HTRQ and HACK/HRRQ handshake flags are provided for polled or interrupt-driven data transfers with the host processor. Because of the speed of the DSP56309 interrupt response, most host microprocessors can load or store data at their maximum programmed I/O instruction rate without testing the handshake flags for each transfer. If full handshake is not needed, the host processor can treat the DSP56309 as a fast device, and data can be transferred between the host processor and the DSP56309 at the fastest host processor data rate. One of the most innovative features of the host interface is the host command feature. With this feature, the host processor can issue vectored interrupt requests to the DSP56309. The host can select any of 128 DSP interrupt routines for execution by writing a vector address register in the HI08. This flexibility allows the host processor to execute up to 128 pre-programmed functions inside the DSP56309. For example, use of the DSP56309 host interrupts can allow the host processor to read or write DSP registers (X, Y, or program memory locations), force interrupt handlers (e.g., SSI, SCI, IRQA, IRQB interrupt routines), and perform control and debugging operations. Note: When the DSP enters stop mode, the HI08 signals are electrically disconnected internally, thus disabling the HI08 until the core leaves stop mode. While the HI08 configuration remains unchanged in stop mode, the core cannot be restarted via the HI08 interface. Do not issue a STOP command to the DSP via the HI08 unless some other mechanism for exiting stop mode is provided. Freescale Semiconductor, Inc... MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 6-21 Freescale Semiconductor, Inc. Host Interface (HI08) HI08-External Host ProgrammerOs Model Table 6-7 Host Side Register Map Host Address 0 1 2 3 Big Endian HLEND = 0 ICR CVR ISR IVR 00000000 RXH/TXH RXM/TXM RXL/TXL Little Endian HLEND = 1 ICR CVR ISR IVR 00000000 RXL/TXL RXM/TXM RXH/TXH Receive/Transmit Bytes Interface Control Command Vector Interface Status Interrupt Vector Unused Freescale Semiconductor, Inc... 4 5 6 7 Host Data Bus H0 - H7 Host Data Bus H0 - H7 6.6.1 Interface Control Register (ICR) The ICR is an 8-bit, read/write control register by which the host processor controls the HI08 interrupts and flags. It is illustrated in Figure 6-12. The DSP core cannot access the ICR. The ICR is a read/write register, which allows the use of bit manipulation instructions on control register bits. The control bits are described in the following paragraphs. 7 INIT 6 5 HLEND 4 HF1 3 HF0 2 HDRQ 1 TREQ 0 RREQ NReserved bit. Read as 0. Should be written with 0, for future compatibility. AA0668 Figure 6-12 Interface Control Register 6-22 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Host Interface (HI08) HI08-External Host ProgrammerOs Model 6.6.1.1 ICR Receive Request Enable (RREQ) Bit 0 The RREQ bit controls the HREQ signal for host receive data transfers. RREQ enables host requests via the host request (HREQ or HRRQ) signal when the receive data register full (RXDF) status bit in the ISR is set. If RREQ is cleared, RXDF interrupts are disabled. If RREQ and RXDF are set, the host request signal (HREQ or HRRQ) is asserted. 6.6.1.2 ICR Transmit Request Enable (TREQ) Bit 1 TREQ enables host requests via the host request (HREQ or HTRQ) signal when the transmit data register empty (TXDE) status bit in the ISR is set. If TREQ is cleared, TXDE interrupts are disabled. If TREQ and TXDE are set, the host request signal is asserted. Freescale Semiconductor, Inc... Table 6-8 and Table 6-9 summarize the effect of RREQ and TREQ on the HREQ and HRRQ signals. Table 6-8 TREQ and RREQ modes (HDRQ = 0) TREQ 0 0 1 1 RREQ 0 1 0 1 HREQ Signal No Interrupts (Polling) RXDF Request (Interrupt) TXDE Request (Interrupt) RXDF and TXDE Request (Interrupts) Table 6-9 TREQ and RREQ modes (HDRQ = 1) TREQ 0 0 1 1 RREQ 0 1 0 1 HTRQ Single No Interrupts (Polling) No Interrupts (Polling) TXDE Request (Interrupt) TXDE Request (Interrupt) HRRQ Signal No Interrupts (Polling) RXDF Request (Interrupt) No Interrupts (Polling) RXDF Request (Interrupt) 6.6.1.3 ICR Double Host Request (HDRQ) Bit 2 If cleared, the HDRQ bit configures HREQ/HTRQ and HACK/HRRQ as HREQ and HACK, respectively. If HDRQ is set, HREQ/HTRQ and HACK/HRRQ are configured as HTRQ and HRRQ, respectively. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 6-23 Freescale Semiconductor, Inc. Host Interface (HI08) HI08-External Host ProgrammerOs Model 6.6.1.4 ICR Host Flag 0 (HF0) Bit 3 The HF0 bit is a general-purpose flag for host-to-DSP communication. The host processor can set or clear HF0, and the DSP56309 cannot change this bit. HF0 is reflected in the HSR on the DSP side of the HI08. 6.6.1.5 ICR Host Flag 1 (HF1) Bit 4 The HF1 bit is a general-purpose flag for host-to-DSP communication. The host processor can set or clear HF1, and the DSP56309 cannot change this bit. HF1 is reflected in the HSR on the DSP side of the HI08. Freescale Semiconductor, Inc... 6.6.1.6 ICR Host Little Endian (HLEND) Bit 5 If the HLEND bit is cleared, the host can access the HI08 in big endian byte order. If set, the host can access the HI08 in little endian byte order. If the HLEND bit is cleared the RXH/TXH register is located at address $5, the RXM/TXM register at $6, and the RXL/TXL register at $7. If the HLEND bit is set, the RXH/TXH register is located at address $7, the RXM/TXM register at $6, and the RXL/TXL register at $5. 6.6.1.7 ICR Reserved Bit 6 This bit is reserved. It is read as 0 and should be written with 0. 6.6.1.8 ICR Initialize Bit (INIT) Bit 7 The host processor uses the INIT bit to force initialization of the HI08 hardware. During initialization, the HI08 transmit and receive control bits are configured. Using the INIT bit to initialize the HI08 hardware may or may not be necessary, depending on the software design of the interface. 6-24 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Host Interface (HI08) HI08-External Host ProgrammerOs Model The tOype of initialization done when the INIT bit is set depends on the state of TREQ and RREQ in the HI08. The INIT command, which is local to the HI08, can conveniently configure the HI08 into the desired data transfer mode. The effect of the INIT command is described in Table 6-10. When the host sets the INIT bit, the HI08 hardware executes the INIT command. The interface hardware clears the INIT bit after the command has been executed. Table 6-10 INIT Command Effects TREQ RREQ 0 1 0 1 After INIT Execution INIT = 0 INIT = 0; RXDF = 0; HTDE = 1 INIT = 0; TXDE = 1; HRDF = 0 INIT = 0; RXDF = 0; HTDE = 1; TXDE = 1; HRDF = 0 Transfer Direction Initialized None DSP to Host Host to DSP Host to/from DSP Freescale Semiconductor, Inc... 0 0 1 1 6.6.2 Command Vector Register (CVR) The host processor uses the CVR to cause the DSP56309 to execute an interrupt. The host command feature is independent of any of the data transfer mechanisms in the HI08. It can cause any of the 128 possible interrupt routines in the DSP core to be executed. This register is illustrated in Figure 6-13. 7 HC 6 HV6 5 HV5 4 HV4 3 HV3 2 HV2 1 HV1 0 HV0 AA0669 Figure 6-13 Command Vector Register (CVR) 6.6.2.1 CVR Host Vector (HV[6:0]) Bits 06 The seven HV bits select the host command interrupt address to be used by the host command interrupt logic. When the host command interrupt is recognized by the DSP interrupt control logic, the address of the interrupt routine taken is 2 HV. The host can write HC and HV in the same write cycle. The host processor can select any of the 128 possible interrupt routine starting addresses in the DSP by writing the interrupt routine address divided by two into the HV bits. This means that the host processor can force any of the existing interrupt handlers (SSI, SCI, MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 6-25 Freescale Semiconductor, Inc. Host Interface (HI08) HI08-External Host ProgrammerOs Model IRQA, IRQB, etc.) and can use any of the reserved or otherwise unused addresses (provided they have been pre-programmed in the DSP). HV is set to $32 (vector location $0064) by a hardware RESET signal, software RESET instruction, individual reset, or a STOP instruction. 6.6.2.2 CVR Host Command Bit (HC) Bit 7 The host processor uses the HC bit to handshake the execution of host command interrupts. Normally, the host processor sets HC to request a host command interrupt from the DSP56309. When the DSP56309 acknowledges the host command interrupt, the HI08 hardware clears the HC bit. The host processor can read the state of HC to determine when the host command has been accepted. After setting HC, the host must not write to the CVR again until the HI08 hardware clears HC. Setting the HC bit causes host command pending (HCP) to be set in the HSR. The host can write to the HC and HV bits in the same write cycle. Freescale Semiconductor, Inc... 6.6.3 Interface Status Register (ISR) The interface status register (ISR) is an 8-bit, read-only status register used by the host processor to interrogate the status and flags of the HI08. The host processor can write to this address without affecting the internal state of the HI08. The DSP core cannot access the ISR. The ISR bits are described in the following paragraphs. This register is illustrated in Figure 6-14. 7 HREQ 6 5 4 HF3 3 HF2 2 TRDY 1 TXDE 0 RXDF NReserved bit. Read as 0. Should be written with 0, for future compatibility. AA0670 Figure 6-14 Interface Status Register 6.6.3.1 ISR Receive Data Register Full (RXDF) Bit 0 The RXDF bit indicates that the receive byte registers (RXH:RXM:RXL) contain data from the DSP56309 and can be read by the host processor. RXDF is set when the HTX is transferred to the receive byte registers. RXDF is cleared when the receive data (RXL or RXH according to HLEND bit) register is read by the host processor. RXDF can be cleared by the host processor using the initialize function. RXDF can assert the external HREQ signal if the RREQ bit is set. Regardless of whether the RXDF interrupt is enabled, RXDF indicates whether the RX registers are full and data can be latched out so that the host processor can use polling techniques. 6-26 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Host Interface (HI08) HI08-External Host ProgrammerOs Model 6.6.3.2 ISR Transmit Data Register Empty (TXDE) Bit 1 The TXDE bit indicates that the transmit byte registers (TXH:TXM:TXL) are empty and can be written by the host processor. TXDE is set when the contents of the transmit byte registers are transferred to the HRX register. TXDE is cleared when the transmit (TXL or TXH according to HLEND bit) register is written by the host processor. The host processor can set TXDE using the initialize function. TXDE can assert the external HTRQ signal if the TREQ bit is set. Regardless of whether the TXDE interrupt is enabled, TXDE indicates whether the TX registers are full and data can be latched in so that the host processor can use polling techniques. Freescale Semiconductor, Inc... 6.6.3.3 ISR Transmitter Ready (TRDY) Bit 2 The TRDY status bit indicates that TXH:TXM:TXL, and the HRX registers are empty. TRDY = TXDE and HRDF If TRDY is set, the data that the host processor writes to TXH:TXM:TXL is immediately transferred to the DSP side of the HI08. This feature has many applications. For example, if the host processor issues a host command which causes the DSP56309 to read the HRX, the host processor can be guaranteed that the data it just transferred to the HI08 is that being received by the DSP56309. 6.6.3.4 ISR Host Flag 2 (HF2) Bit 3 HF2 indicates the state of host flag 2 in the HCR on the DSP side. HF2 can be changed only by the DSP56309, as documented in Section 6.5.3.4NHCR Host Flags 2,3 (HF[3:2]) Bits 3, 4 on page 6-10. 6.6.3.5 ISR Host Flag 3 (HF3) Bit 4 HF3 indicates the state of Host Flag 3 in the HCR on the DSP side. HF3 can be changed only by the DSP56309, as documented in Section 6.5.3.4NHCR Host Flags 2,3 (HF[3:2]) Bits 3, 4 on page 6-10. 6.6.3.6 ISR Reserved Bits 5, 6 These bits are reserved. They are read as 0 and should be written with 0. 6.6.3.7 ISR Host Request (HREQ) Bit 7 HREQ indicates the status of the external transmit and receive request output signals (HTRQ and HRRQ) if HDRQ is set. If HDRQ is cleared, it indicates the status of the external host request output signal (HREQ). Table 6-11 shows possible settings of HRDQ and HDEQ and their effects. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 6-27 Freescale Semiconductor, Inc. Host Interface (HI08) HI08-External Host ProgrammerOs Model Table 6-11 HREQ and HDRQ Settings HDRQ 0 0 1 1 HREQ 0 1 0 1 Effect HREQ is cleared; no host processor interrupts are requested. HREQ is set; an interrupt is requested. HTRQ and HRRQ are cleared, no host processor interrupts are requested. HTRQ or HRRQ are set; an interrupt is requested. Freescale Semiconductor, Inc... The HREQ is set from either or both of two conditionsNeither the receive byte registers are full or the transmit byte registers are empty. These conditions are indicated by the ISR RXDF and TXDE status bits, respectively. If the interrupt source has been enabled by the associated request enable bit in the ICR, HREQ is set if one or more of the two enabled interrupt sources is set. 6.6.4 Interrupt Vector Register (IVR) The IVR is an 8-bit, read/write register which typically contains the interrupt vector number used with MC68000 family processor vectored interrupts. Only the host processor can read and write this register. The contents of the IVR are placed on the host data bus, H[7:0], when both the HREQ and HACK signals are asserted. The contents of this register are initialized to $0F by a hardware RESET signal or software RESET instruction. This value corresponds to the uninitialized interrupt vector in the MC68000 family. This register is illustrated in Figure 6-15. 7 IV7 6 IV6 5 IV5 4 IV4 3 IV3 2 IV2 1 IV1 0 IV0 AA0671 Figure 6-15 Interrupt Vector Register (IVR) 6.6.5 Receive Byte Registers (RXH: RXM: RXL) The receive byte registers are viewed by the host processor as three 8-bit, read-only registers. These registers are the receive high register (RXH), the receive middle register (RXM), and the receive low register (RXL). They receive data from the high, middle, and 6-28 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Host Interface (HI08) HI08-External Host ProgrammerOs Model low bytes, respectively, of the HTX register and are selected by the external host address inputs (HA[2:0]) during a host processor read operation. The memory address of the receive byte registers is set by the HLEND bit in the ICR. If the HLEND bit is set, the RXH is located at address $7, RXM at $6, and RXL at $5. If the HLEND bit is cleared, the RXH is located at address $5, RXM at $6, and RXL at $7. When data is written to the receive byte register at host address $7, the receive data register full (RXDF) bit is set. The host processor can program the RREQ bit to assert the external HREQ signal when RXDF is set. This indicates that the HI08 has a full word (either 8, 16, or 24 bits) for the host processor. The host processor can program the RREQ bit to assert the external HREQ signal when RXDF is set. Asserting the HREQ signal informs the host processor that the receive byte registers have data to be read. When the host reads the receive byte register at host address $7, the RXDF bit is cleared. Freescale Semiconductor, Inc... 6.6.6 Transmit Byte Registers (TXH:TXM:TXL) The host processor views the transmit byte registers as three 8-bit, write-only registers. These registers are the transmit high register (TXH), the transmit middle register (TXM), and the transmit low register (TXL). These registers send data to the high, middle, and low bytes, respectively, of the HRX register and are selected by the external host address inputs, HA[2:0], during a host processor write operation. If the HLEND bit in the ICR is set, the TXH register is located at address $7, the TXM register at $6 and the TXL register at $5. If the HLEND bit in the ICR is cleared, the TXH register is located at address $5, the TXM register at $6, and the TXL register at $7. Data is written into the transmit byte registers when the transmit data register empty (TXDE) bit is set. The host processor programs the TREQ bit to assert the external HREQ/HTRQ signal when TXDE is set. This informs the host processor that the transmit byte registers are empty. Writing to the data register at host address $7 clears the TXDE bit. The contents of the transmit byte registers are transferred as 24-bit data to the HRX register when both the TXDE and the HRDF bit are cleared. This transfer operation sets TXDE and HRDF. Note: When data is written to a peripheral device, there is a two-cycle pipeline delay until any status bits affected by this operation are updated. If you read any of those status bits within the next two cycles, the bit does not reflect its current status. See the DSP56300 Family Manual, Appendix B, Polling a Peripheral Device for Write for further details. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 6-29 Freescale Semiconductor, Inc. Host Interface (HI08) HI08-External Host ProgrammerOs Model 6.6.7 Host Side Registers After Reset Table 6-12 shows the result of the four kinds of reset on bits in each of the HI08 registers seen by the host processor. The hardware reset is caused by asserting the RESET signal. The software reset is caused by executing the RESET instruction. The individual reset is caused by clearing the HEN bit in the HPCR. The stop reset is caused by executing the STOP instruction. Table 6-12 Host Side Registers After Reset Freescale Semiconductor, Inc... Reset Type Register Name ICR CVR Register Data All Bits HC HV[0:6] ISR HREQ HF3 -HF2 TRDY TXDE RXDF IVR RX TX IV[0:7] RXH: RXM:RXL TXH: TXM:TXL HW Reset 0 0 $32 0 0 1 1 0 $0F empty empty SW Reset 0 0 $32 0 0 1 1 0 $0F empty empty IR Reset N 0 N 1 if TREQ is set; 0 otherwise N 1 1 0 N empty empty ST Reset N 0 N 1 if TREQ is set; 0 otherwise N 1 1 0 N empty empty 6.6.8 General-Purpose I/O When configured as GPIO, the HI08 is viewed by the DSP56309 as memory-mapped registers, as documented in Section 6.5NHI08 DSP Side ProgrammerOs Model on page 6-8. Those memory-mapped registers control up to 16 I/O signals. Software RESET instructions and hardware RESET signals clear all DSP side control registers and configure the HI08 as GPIO with all 16 signals disconnected. External circuitry 6-30 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Host Interface (HI08) Servicing the Host Interface connected to the HI08 may need external pull-up/pull-down resistors until the signals are configured for operation. The registers cleared are the HPCR, HDDR, and HDR. Selection between GPIO and HI08 is made by clearing HPCR bits 6 through 1 for GPIO or setting these bits for HI08 functionality. If the HI08 is in GPIO mode, the HDDR configures each corresponding signal in the HDR as an input signal if the HDDR bit is cleared or as an output signal if the HDDR bit is set. (See Section 6.5.7NHost Data Direction Register (HDDR) on page 6-17 and Section 6.5.8NHost Data Register (HDR) also on page 6-17.) Freescale Semiconductor, Inc... 6.7 SERVICING THE HOST INTERFACE The HI08 can be serviced by using one of the following protocols: Polling Interrupts The host processor writes to the appropriate HI08 register to reset the control bits and configure the HI08 for proper operation. 6.7.1 HI08 Host Processor Data Transfer To the host processor, the HI08 looks like a contiguous block of Static RAM. To transfer data between itself and the HI08, the host processor performs the following steps: 1. asserts the HI08 address to select the register to be read or written 2. selects the direction of the data transfer (If it is writing, the host processor sources the data on the bus.) 3. strobes the data transfer 6.7.2 Polling In polling mode, the HREQ/HTRQ signal is not connected to the host processor and HACK must be deasserted to insure IVR data is not being driven on H[7:0] when other registers are being polled. (If the HACK function is not needed, the HACK signal can be configured as a GPIO signal, as documented in Section 6.5.6NHost Port Control Register (HPCR) on page 6-12.) MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 6-31 Freescale Semiconductor, Inc. Host Interface (HI08) Servicing the Host Interface The host processor first performs a data read transfer to read the ISR, as in Figure 6-16. This convention allows the host processor to assess the status of the HI08 and perform the appropriate actions. Generally, after the appropriate data transfer has been made, the corresponding status bit is updated to reflect the transfer. If RXDF is set, the receive data register is full, and the host processor can perform a data read. Freescale Semiconductor, Inc... If TXDE is set, the transmit data register is empty, and the host processor can perform a data write. If TRDY is set, the transmit data register is empty. This implies that the receive data register on the DSP side is also empty. Data written by the host processor to the HI08 is transferred directly to the DSP side. If (HF2 and HF3) 0, depending on how the host flags have been used, this may indicate that an application-specific state within the DSP56309 has been reached. Intervention by the host processor may be required. If HREQ is set, the HREQ/TRQ signal has been asserted, and the DSP56309 is requesting the attention of the host processor. One of the previous four conditions exists. After the appropriate data transfer has been made, the corresponding status bit is updated to reflect the transfer. If the host processor has issued a command to the DSP56309 by writing to the CVR and setting the HC bit, it can read the HC bit in the CVR to determine whether the command has been accepted by the interrupt controller in the DSP core. When the command has been accepted for execution, the HC bit is cleared by the interrupt controller in the DSP core. 6.7.3 Servicing Interrupts If either HREQ/HTRQ or the HRRQ signal or both are connected to the host processorOs interrupt input, the HI08 can request service from the host processor by asserting one of these signals. The HREQ/HTRQ and/or the HRRQ signal is asserted when TXDE is set and/or RXDF is set and the corresponding enable bit (TREQ or RREQ, respectively) is set. This situation appears in Figure 6-16. 6-32 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Host Interface (HI08) Servicing the Host Interface 7 $2 HREQ 0 0 HF3 HF2 TRDY Status TXDE RXDF 0 ISR Host Request Asserted HRRQ HREQ HTRQ 7 $0 INIT 0 0 HF1 HF0 HBEND TREQ 0 RREQ ICR AA0672 Freescale Semiconductor, Inc... Enable Figure 6-16 HI08 Host Request Structure HREQ is normally connected to the maskable interrupt input of the host processor. The host processor acknowledges host interrupts by executing an interrupt service routine. The host processor can test the two LSBs (RXDF and TXDE) of the ISR register to determine the interrupt source, as in Figure 6-16. The host processor interrupt service routine must read or write the appropriate HI08 data register to clear the interrupt. HREQ/HTRQ and/or HRRQ is deasserted under either of the following conditions: The enabled request is cleared or masked. The DSP is reset. If the host processor is a member of the MC68000 family, there is no need for the additional step when the host processor reads the ISR to determine how to respond to an interrupt generated by the DSP56309. Instead, the DSP56309 automatically sources the contents of the IVR on the data bus when the host processor acknowledges the interrupt by asserting HACK. The contents of the IVR are placed on the host data bus while HREQ/TRQ (or HRRQ) and HACK are simultaneously asserted. The IVR data tells the MC680XX host processor which interrupt routine to execute to service the DSP56309. Table 6-13 shows the HI08 programming model. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 6-33 Freescale Semiconductor, Inc... 6.8 Table 6-13 HI08 Programming Model Bit Comments Mnemonic DSP SIDE HRIE Receive Interrupt Enable Transmit Interrupt Enable Host Command Interrupt Enable Host Flag 2 Host Flag 3 Host GPIO Enable 0 1 0 1 HA8/A1 = GPIO HA8/A1 = HA8 GPIO signal disconnected GPIO signals active 0 1 HCP interrupt disabled HCP interrupt enabled 0 1 HTRQ interrupt disabled HTRQ interrupt enabled 0 1 HRRQ interrupt disabled HRRQ interrupt enabled HI08 PROGRAMMING MODEL QUICK REFERENCE 6-34 Reset Type Function HW/ SW IS RT Name Value N N N N N N This bit is treated as 1 if HMUX = 0. This bit is treated as 0 if HEN = 0. This bit is treated as 1 if HMUX = 0. This bit is treated as 0 if HEN = 0. HCS/A10 = GPIO HCS/A10 = HCS This bit is treated as 0 if HEN = 0. 0 N N HTIE 0 N N HCIE 0 N N HF2 HF3 HGEN Reg Host Interface (HI08) # HCR 0 1 HI08 Programming Model Quick Reference 2 3 N N N N 0 0 0 N N N N N N Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com HA8EN Host Address Line 8 Enable HA9EN Host Address Line 9 Enable 0 1 HA9/A2 = GPIO HA9/A2 = HA9 HCSEN Host Chip Select Enable 0 1 DSP56309UM/D 4 HPCR 0 1 0 N N 2 0 N N MOTOROLA 3 0 N N Freescale Semiconductor, Inc... Table 6-13 HI08 Programming Model (Continued) Bit Comments Mnemonic HREN Host Request Enable 0 HREQ/HTRQ = GPIO HREQ/HTRQ HACK/HRRQ = GPIO HREQ/HTRQ = HREQ,HREQ/HTRQ HACK/HRRQ = HTRQ, HRRQ HDRQ = 0 HDRQ=1 0 HACK/HRRQ = GPIO HREQ/HTRQ HACK/HRRQ = GPIO This bit is ignored if HDRQ = 1. This bit is treated as 0 if HREN = 0. This bit is treated as 0 if HEN = 0. 0 N N HDRQ = 0 HDRQ = 1 Reset Type Function N 0 Reg Name Value HW/ SW MOTOROLA IS RT N N 1 HAEN Host Acknowledge Enable 1 HEN Host Enable 0 1 0 1 0 1 0 1 0 1 0 1 Host Port = GPIO Host Port Active HREQ/HTRQ/HRRQ = driven HREQ/HTRQ/HRRQ = open drain HDS/HRD/HWR active low HDS/HRD/HWR active high HAS active low HAS active high Separate address and data lines Multiplexed address/data Single Data Strobe (HDS) Double Data Strobe (HWR, HRD) HACK/HRRQ = HACK HREQ/HTRQ HACK/HRRQ = HTRQ, HRRQ # HPCR 4 5 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com DSP56309UM/D HROD Host Request Open Drain Host Data Strobe Polarity Host Address Strobe Polarity Host Multiplexed Bus Host Dual Data Strobe HDSP HASP HMUX HDDS 6 N This bit is ignored if HEN = 0. This bit is ignored if HEN = 0. This bit is ignored if HEN = 0. This bit is ignored if HEN = 0. This bit is ignored if HEN = 0. 0 N N 8 0 9 0 N N 10 0 N N 11 0 N N 12 0 N N Host Interface (HI08) HI08 Programming Model Quick Reference 6-35 Freescale Semiconductor, Inc... Table 6-13 HI08 Programming Model (Continued) Bit Comments Mnemonic HCSP Host Chip Select Polarity Host Request polarity Host Acknowledge Polarity Host Receive Data Full Host Transmit Data Empty Host Command Pending Host Flag 0 Host Flag 1 Host Base Address Register DSP Receive Data Register DSP Transmit Data Register GPIO signal Data GPIO signal Direction [0] [1] 0 1 no host command pending host command pending 1 0 The Transmit Data Register is empty. The Transmit Data Register is not empty. 0 1 no receive data to be read Receive Data Register is full 0 1 HACK active low HACK active high This bit is ignored if HEN = 0. 0 1 HREQ/HTRQ/HRRQ active low HREQ/HTRQ/HRRQ active high This bit is ignored if HEN = 0. 0 0 1 HCS active low HCS active high This bit is ignored if HEN = 0. 0 6-36 Reset Type Function HW/ SW N Reg Name Value # IS RT N Host Interface (HI08) HPCR 13 14 HRP N N 15 HAP 0 N N HSR 0 HRDF N N N N N 0 0 0 HI08 Programming Model Quick Reference 1 HTDE 1 1 1 2 HCP 0 0 0 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com HF0 HF1 BA10-BA3 DSP56309UM/D N N N N N N Input Output 3 N N N N N N 0 0 N N N N 4 HBAR 7-0 N N N N N $80 N N HRX 23-0 N N D16-D0 DR16-DR0 empty N N HTX 23-0 empty N N HDR 16-0 $0000 $0000 N N N N MOTOROLA HDRR 16-0 Freescale Semiconductor, Inc... Table 6-13 HI08 Programming Model (Continued) Bit Comments Mnemonic HOST SIDE RREQ Receive Request Enable Transmit Request Enable Double Host Request 1 0 HREQ/HTRQ = HREQ, HACK/HRRQ = HACK HREQ/HTRQ = HTRQ, HACK/HRRQ = HRRQ 0 1 HTRQ interrupt disabled HTRQ interrupt enabled 0 1 HRRQ interrupt disabled HRRQ interrupt enabled Reset Type Function HW/ SW IS RT Reg Name Value MOTOROLA N N N 0 N N TREQ 0 N N HDRQ 0 N N HF0 HF1 HLEND Host Little Endian 0 1 1 Big Endian order Little Endian order Reset data paths according to TREQ and RREQ Host Flag 1 Host Flag 0 # ICR 0 1 2 3 N N N N N N N cleared by HI08 hardware 0 0 0 N N N N N N 4 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com INIT Initialize DSP56309UM/D 5 7 0 N N Host Interface (HI08) HI08 Programming Model Quick Reference 6-37 Freescale Semiconductor, Inc... Table 6-13 HI08 Programming Model (Continued) Bit Comments Mnemonic RXDF Receive Data Register Full Transmit Data Register Empty Transmitter Ready 1 0 transmit FIFO (6 deep) is empty transmit FIFO is not empty 1 0 Host Transmit Register is empty Host Transmit Register is full 0 1 Host Receive Register is empty Host Receive Register is full 6-38 Reset Type Function N 0 0 Reg Name Value HW/ SW # IS RT 0 Host Interface (HI08) ISR 0 1 TXDE N N N N N default vector via programmable cleared by HI08 hardware when the HC interrupt request is serviced 1 1 1 2 TRDY 1 1 1 3 HF3 HREQ Host Request 0 1 HREQ signal is deasserted HREQ signal is asserted (if enabled) Host Flag 3 HF2 Host Flag 2 N N N N 0 0 0 N N 0 N N 0 HI08 Programming Model Quick Reference 4 7 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com HV6-HV0 Host Command Vector Host Command 0 1 no host command pending host command pending DSP56309UM/D N N HC CVR 6-0 $32 N N CVR 7 0 0 0 RXH/M/L 7-0 N Host Receive Data Register Host Transmit Data Register Interrupt Register N N N N N 68000 family vector register N N N empty NN empty N N TXH/M/L 7-0 N IV7-IV0 MOTOROLA IVR 7-0 $0F N N Freescale Semiconductor, Inc. SECTION 7 Freescale Semiconductor, Inc... ENHANCED SYNCHRONOUS SERIAL INTERFACE (ESSI) MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 7-1 Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) 7.1 7.2 7.3 7.4 7.5 7.6 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 ENHANCEMENTS TO THE ESSI . . . . . . . . . . . . . . . . . . . . . 7-3 ESSI DATA AND CONTROL SIGNALS . . . . . . . . . . . . . . . . 7-4 ESSI PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . 7-8 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36 GPIO SIGNALS AND REGISTERS. . . . . . . . . . . . . . . . . . . 7-43 Freescale Semiconductor, Inc... 7-2 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) Introduction 7.1 INTRODUCTION The Enhanced Synchronous Serial Interface (ESSI) provides a full-duplex serial port for serial communication with a variety of serial devices, including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals that implement the Motorola Serial Peripheral Interface (SPI). The ESSI consists of independent transmitter and receiver sections and a common ESSI clock generator. There are two independent and identical ESSIs in the DSP56309: ESSI0 and ESSI1. For the sake of simplicity, a single generic ESSI is described. Freescale Semiconductor, Inc... The ESSI block diagram appears in Figure 7-1 on page 7-5. This interface is synchronous because all serial transfers are synchronized to a clock. Note: This should not be confused with the asynchronous mode of the ESSI, in which separate clocks are used for the receiver and transmitter. In this mode, the ESSI is still a synchronous device, because all transfers are synchronized to these clocks. Additional synchronization signals are used to delineate the word frames. Normal mode is used to transfer data at a periodic rate, one word per period. Network mode is similar in that it is also intended for periodic transfers; however, it supports up to 32 words (time slots) per period. Network mode can be used to build time division multiplexed (TDM) networks. In contrast, on-demand mode is intended for non-periodic transfers of data. This mode can be used to transfer data serially at high speed when the data become available. This mode offers a subset of the SPI protocol. Since each ESSI unit can be configured with one receiver and three transmitters, the two units can be used together for surround sound applications (which need two digital input channels and six digital output channels). 7.2 ENHANCEMENTS TO THE ESSI The synchronous serial interface (SSI) used in the DSP56000 family has been enhanced in the following ways to make the ESSI: Network enhancements Time slot mask registers (receive and transmit) added End-of-frame interrupt added Drive enable signal added (to be used with transmitter 0) MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 7-3 Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) ESSI Data and Control Signals Audio enhancements Three transmitters per ESSI (for six-channel surround sound) Can trigger DMA interrupts (receive or transmit) Separate exception enable bits One divide by 2 removed from the internal clock source chain CRA (PSR) bit definition is reversed Gated clock mode not available General enhancements Other Changes Freescale Semiconductor, Inc... 7.3 ESSI DATA AND CONTROL SIGNALS Three to six signals are required for ESSI operation, depending on the operating mode selected. The serial transmit data (STD) signal and serial control (SC0 and SC1) signals are fully synchronized to the clock if they are programmed as transmit-data signals. 7.3.1 Serial Transmit Data (STD) Signal The STD signal is used for transmitting data from the TX0 serial transmit shift register. STD is an output when data is being transmitted from the TX0 shift register. With an internally generated bit clock, the STD signal becomes a high impedance output signal for a full clock period after the last data bit has been transmitted. If sequential data words are being transmitted, the STD signal does not assume a high-impedance state. The STD signal can be programmed as a GPIO signal (P5) when the ESSI STD function is not being used. 7.3.2 Serial Receive Data Signal (SRD) The SRD signal receives serial data and transfers the data to the ESSI receive shift register. SRD can be programmed as a GPIO signal (P4) when the ESSI SRD function is not being used. The ESSI block diagram is shown in Figure 7-1. 7-4 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) ESSI Data and Control Signals GDB DDB RCLK RSMA RSMB RX RX SHIFT REG SRD TSMA TCLK TX0 SHIFT REG STD Freescale Semiconductor, Inc... TSMB TX0 CRA TX1 SHIFT REG CRB SC0 TX1 TSR TX2 SHIFT REG SC1 SSISR TX2 Interrupts Clock/Frame Sync Generators and Control Logic SC2 SCK AA0678 Figure 7-1 ESSI Block Diagram 7.3.3 Serial Clock (SCK) The SCK signal is a bidirectional signal providing the serial bit rate clock for the ESSI interface. The SCK signal is a clock input or output used by all the enabled transmitters and receiver in synchronous modes or by all the enabled transmitters in asynchronous MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 7-5 Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) ESSI Data and Control Signals modes; see Table 7-1 on page 7-8. SCK can be programmed as a GPIO signal (P3) when the ESSI SCK function is not being used. Notes: 1. Although an external serial clock can be independent of and asynchronous to the DSP system clock, the external ESSI clock frequency must not exceed Fcore/3, and each ESSI phase must exceed the minimum of 1.5 CLKOUT cycles. 2. The internally sourced ESSI clock frequency must not exceed Fcore/4. Freescale Semiconductor, Inc... 7.3.4 Serial Control Signal (SC0) SC00 is a serial control signal for ESSI0, and SC10 is a serial control signal for ESSI1. They are referred to collectively as SC0. The function of this signal is determined by selecting either synchronous or asynchronous mode; see Table 7-4 on page 7-24. In asynchronous mode, this signal is used for the receive clock I/O. In synchronous mode, this signal is used as the transmitter data out signal for transmit shift register 1 or for serial flag I/O. A typical application of serial flag I/O would be multiple device selection for addressing in codec systems. If SC0 is configured as a serial flag signal, its direction is determined by the serial control direction 0 (SCD0) bit in the ESSI control register B (CRB). When configured as an output, its value is determined by the value of the serial output flag 0 (OF0) bit in the CRB. When configured as an input, SC0 controls the state of serial input flag 0 (IF0) bit in the ESSI status register (SSISR). When SC0 is configured as a transmit data signal, it is always an output signal regardless of the SCD0 bit value. SC0 is fully synchronized with the other transmit data signals (STD and SC1). In asynchronous mode, SC0 is configured as the receive clock. The direction of the SC0 in this mode is also determined by SCD0. SC0 can be programmed as a GPIO signal (P0) when the ESSI SC0 function is not being used. Note: The ESSI can operate with more than one active transmitter only in synchronous mode. 7-6 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) ESSI Data and Control Signals 7.3.5 Serial Control Signal (SC1) SC01 is a serial control signal for ESSI0, and SC11 is a serial control signal for ESSI1. They are referred to collectively as SC1. The function of this signal is determined by selecting either synchronous or asynchronous mode; see Table 7-4 on page 7-24. In asynchronous mode (such as a single codec with asynchronous transmit and receive), SC1 is the receiver frame sync I/O. In synchronous mode, SC1 is used for the transmitter data out signal of transmit shift register TX2, for the drive enable transmitter 0 signal, or for serial flag SC1. Freescale Semiconductor, Inc... When used as a serial flag signal, SC1 operates like the previously described SC0. SC0 and SC1 are independent flags but can be used together for multiple serial device selection. SC0 and SC1 can be used unencoded to select up to two codecs or can be decoded externally to select up to four codecs. If SC1 is configured as a serial flag signal, its direction is determined by the SCD1 bit in the CRB. When configured as an output, its value is determined by the value of the serial output flag1 (OF1) bit in the CRB. When configured as an input, SC0 controls the stated serial input flag 1 (IF1) bits in SSISR. When SC1 is configured as a transmit data signal, it is always an output signal regardless of the SCD1 bit value. As an output, it is fully synchronized with the other ESSI transmit data signals (STD and SC0). In asynchronous mode, SC1 is configured as the receive frame sync. The direction of SC1 in this mode is determined by SCD1. SC1 can be programmed as a GPIO signal (P1) when the ESSI SC1 function is not being used. Table 7-1 summarizes ESSI clock sources, whether synchronous or asynchronous, and shows the bit settings for the signals involved. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 7-7 Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) ESSI Programming Model Table 7-1 ESSI Clock Sources SYN SCKD SCD0 R Clock Source RX Clock Out T Clock Source TX Clock Out Asynchronous 0 0 0 0 1 1 0 1 0 1 EXT, SC0 INT EXT, SC0 INT N SC0 N SC0 EXT, SCK EXT, SCK INT INT N N SCK SCK Freescale Semiconductor, Inc... 0 0 Synchronous 1 1 0 1 0/1 0/1 EXT, SCK INT N SCK EXT, SCK INT N SCK 7.3.6 Serial Control Signal (SC2) SC02 is a serial control signal for ESSI0, and SC12 is a serial control signal for ESSI1. They are referred to collectively as SC2. This signal is used for frame sync I/O. SC2 is the frame sync for both the transmitter and receiver in synchronous mode and for the transmitter only in asynchronous mode. The direction of this signal is determined by the SCD2 bit in the CRB. When configured as an output, this signal outputs the internally generated frame sync signal. When configured as an input, this signal receives an external frame sync signal for the transmitter in asynchronous mode and for the receiver when in synchronous mode. SC2 can be programmed as a GPIO signal (P2) when the ESSI SC2 function is not being used. 7.4 ESSI PROGRAMMING MODEL The ESSI includes the following registers: Two control registers (CRA, CRB) illustrated in Figure 7-2 and Figure 7-3 One status register (SSISR) illustrated in Figure 7-4 7-8 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) ESSI Programming Model Three transmit data registers (TX0, TX1, TX2) One receive data register (RX) Two transmit slot mask registers (TSMA, TSMB) illustrated in Figure 7-5 and Figure 7-6 Two receive slot mask registers (RSMA, RSMB) illustrated in Figure 7-7 and Figure 7-8 One special-purpose time slot register (TSR) The following paragraphs give detailed descriptions and operations of each of the bits in the ESSI registers. The GPIO functionality of the ESSI is documented in Section 7.6NGPIO Signals and Registers of this manual. 11 PSR Freescale Semiconductor, Inc... 10 9 8 7 PM7 6 PM6 5 PM5 4 PM4 3 PM3 2 PM2 1 PM1 0 PM0 23 22 SSC1 21 WL2 20 WL1 19 WL0 18 ALC 17 16 DC4 15 DC3 14 DC2 13 DC1 12 DC0 AA0857 Figure 7-2 ESSI Control Register A (CRA) (ESSI0 X:$FFFFB5, ESSI1 X:$FFFFA5) 11 CKP 10 FSP 9 FSR 8 FSL1 7 FSL0 6 SHFD 5 SCKD 4 SCD2 3 SCD1 2 SCD0 1 OF1 0 OF0 23 REIE 22 TEIE 21 RLIE 20 TLIE 19 RIE 18 TIE 17 RE 16 TE0 15 TE1 14 TE2 13 MOD 12 SYN AA0858 Figure 7-3 ESSI Control Register B (CRB) (ESSI0 X:$FFFFB6, ESSI1 X:$FFFFA6) 11 10 9 8 7 RDF 6 TDE 5 ROE 4 TUE 3 RFS 2 TFS 1 IF1 0 IF0 23 22 21 20 19 18 17 16 15 14 13 12 AA0859 Figure 7-4 ESSI Status Register (SSISR) (ESSI0 X:$FFFFB7, ESSI1 X:$FFFFA7) MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 7-9 Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) ESSI Programming Model 11 TS11 10 TS10 9 TS9 8 TS8 7 TS7 6 TS6 5 TS5 4 TS4 3 TS3 2 TS2 1 TS1 0 TS0 23 22 21 20 19 18 17 16 15 TS15 14 TS14 13 TS13 12 TS12 AA0860 Figure 7-5 ESSI Transmit Slot Mask Register A (TSMA) (ESSI0 X:$FFFFB4, ESSI1 X:$FFFFA4) 11 10 TS26 9 TS25 8 TS24 7 TS23 6 TS22 5 TS21 4 TS20 3 TS19 2 TS18 1 TS17 0 TS16 Freescale Semiconductor, Inc... TS27 23 22 21 20 19 18 17 16 15 TS31 14 TS30 13 TS29 12 TS28 AA0861 Figure 7-6 ESSI Transmit Slot Mask Register B (TSMB) (ESSI0 X:$FFFFB3, ESSI1 X:$FFFFA3) 11 RS11 10 RS10 9 RS9 8 RS8 7 RS7 6 RS6 5 RS5 4 RS4 3 RS3 2 RS2 1 RS1 0 RS0 23 22 21 20 19 18 17 16 15 RS15 14 RS14 13 RS13 12 RS12 AA0862 Figure 7-7 ESSI Receive Slot Mask Register A (RSMA) (ESSI0 X:$FFFFB2, ESSI1 X:$FFFFA2) 11 RS27 10 RS26 9 RS25 8 RS24 7 RS23 6 RS22 5 RS21 4 RS20 3 RS19 2 RS18 1 RS17 0 RS16 23 22 21 20 19 18 17 16 15 RS31 14 RS30 13 RS29 12 RS28 Reserved bit - read as zero should be written with zero for future compatibility AA0863 Figure 7-8 ESSI Receive Slot Mask Register B (RSMB) (ESSI0 X:$FFFFB1, ESSI1 X:$FFFFA1) 7-10 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) ESSI Programming Model 7.4.1 ESSI Control Register A (CRA) The ESSI control register A (CRA) is one of two 24-bit, read/write control registers used to direct the operation of the ESSI. The CRA controls the ESSI clock generator bit and frame sync rates, word length, and number of words per frame for the serial data. The CRA control bits are described in the following paragraphs; see also Figure 7-2 on page 7-9. 7.4.1.1 CRA Prescale Modulus Select PM[7:0] Bits 70 The PM[7:0] bits specify the divide ratio of the prescale divider in the ESSI clock generator. A divide ratio from 1 to 256 (PM = $0 to $FF) can be selected. The bit clock output is available at the transmit clock signal (SCK) and/or the receive clock (SC0) signal of the DSP. The bit clock output is also available internally for use as the bit clock to shift the transmit and receive shift registers. The ESSI clock generator functional diagram is shown in Figure 7-9. Fcore is the DSP56309 core clock frequency (the same frequency as the CLKOUT signal, when that signal is enabled). Careful choice of the crystal oscillator frequency and the prescaler modulus allows generation of the industry-standard codec master clock frequencies of 2.048 MHz, 1.544 MHz, and 1.536 MHz. Both the hardware RESET signal and the software RESET instruction clear PM[7:0]. 7.4.1.2 CRA Reserved Bits 810 These bits are reserved. They are read as 0 and should be written with 0. 7.4.1.3 CRA Prescaler Range (PSR) Bit 11 The PSR controls a fixed divide-by-eight prescaler in series with the variable prescaler. This bit is used to extend the range of the prescaler for those cases where a slower bit clock is desired. When PSR is set, the fixed prescaler is bypassed. When PSR is cleared, the fixed divide-by-eight prescaler is operational; see Figure 7-9 on page 7-12. Note: This definition is reversed from that of the 560xx SSI. Freescale Semiconductor, Inc... The maximum allowed internally generated bit clock frequency is the internal DSP56309 clock frequency divided by 4; the minimum possible internally generated bit clock frequency is the DSP56309 internal clock frequency divided by 4096. Both the hardware RESET signal and the software RESET instruction clear PSR. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 7-11 Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) ESSI Programming Model Note: The combination PSR = 1 and PM[7:0] = $00 (dividing Fcore by 2) can cause synchronization problems and should not be used. TX #1 or Flag0 Out CRB(TE1) CRB(OF0) (Sync Mode) Flag0 In SSISR(IF0) (Sync Mode) CRA(WL2:0) /8, /12, /16, /24, /32 CRB(SYN) = 1 SCD0 = 0 SYN = 0 SCD0 = 1 RCLOCK SYN = 1 CRA(WL2:0) TCLOCK /8, /12, /16, /24, /32 0 1 2 3 4,5 TX Word Clock 0 1 2 3 4,5 RX Word Clock Freescale Semiconductor, Inc... Sync: SCn0 TX #1, or Flag0 CRB(SCD0) Async: RX clk RX Shift Register SYN = 0 SCKn Sync: TX/RX clk Async: CRB(SCKD) TX clk CRA(PSR) /2 FCORE /1 or /8 1 0 (Opposite from SSI) Internal Bit Clock TX Shift Register Note: 1. FCORE is the DSP56300 Core internal clock frequency. 2. ESSI internal clock range: min = FOSC/4096 max = FOSC/4 3. OnO in signal name is ESSI # (0 or 1) AA0679 CRA(PM7:0) /1 to /256 0 255 Figure 7-9 ESSI Clock Generator Functional Block Diagram 7.4.1.4 CRA Frame Rate Divider Control DC[4:0] Bits 1612 The values of the DC[4:0] bits control the divide ratio for the programmable frame rate dividers used to generate the frame clocks. In network mode, this ratio can be interpreted as the number of words per frame minus one. In normal mode, this ratio determines the word transfer rate. The divide ratio can range from 1 to 32 (DC = 00000 to 11111) for normal mode and 2 to 32 (DC = 00001 to 11111) for network mode. A divide ratio of one (DC = 00000) in network mode is a special case known as on-demand mode. In normal mode, a divide ratio of one (DC = 00000) provides continuous periodic data word transfers. A bit-length frame sync must be used in this case and is selected by setting the FSL[1:0] bits in the CRA to (01). Both the hardware RESET signal and the software RESET instruction clear DC[4:0]. The ESSI frame sync generator functional diagram is shown in Figure 7-10. 7-12 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) ESSI Programming Model RX Word Clock CRB(FSL1) CRB(FSR) CRA(DC4:0) /1 to /32 0 31 CRB(SCD1) = 1 CRB(SYN) = 0 Receive Control Logic Receive Frame Sync SYN = 1 SCD1 = 0 SYN = 1 SCn1 Sync: TX #2, Flag1, or drive enb. Async: RX F.S. SYN = 0 Sync Type Internal Rx Frame Sync CRB(SCD1) Freescale Semiconductor, Inc... These signals are identical in sync mode. CRB(FSL1:0) CRB(FSR) TX Word Clock Flag1 In SSISR(IF1) (Sync Mode) TX #2, Flag1 Out, or drive enb. CRB(TE2) CRB(OF1) CRA(SSC1) (Sync Mode) CRB(SCD2) CRA(DC4:0) /1 to /32 0 31 Sync Type Internal TX Frame Sync SCn2 Sync: TX/RX F.S. Async: TX F.S. Transmit Control Logic Transmit Frame Sync AA0680 Figure 7-10 ESSI Frame Sync Generator Functional Block Diagram 7.4.1.5 CRA Reserved Bit 17 This bit is reserved. It is read as 0 and should be written with 0. 7.4.1.6 CRA Alignment Control (ALC) Bit 18 The ESSI is designed for 24-bit fractional data. Shorter data words are left aligned to the MSB, Bit 23. For applications that use 16 bit fractional data, shorter data words are left aligned to bit 15. The ALC bit supports shorter data words. If ALC is set, received words are left aligned to bit 15 in the receive shift register. Transmitted words must be left aligned to bit 15 in the transmit shift register. If the ALC bit is cleared, received words are left aligned to bit 23 in the receive shift register. Transmitted words must be left aligned to bit 23 in the transmit shift register. The ALC bit is cleared by either a hardware RESET signal or a software RESET instruction. Note: If the ALC bit is set, only 8-, 12-, or 16-bit words should be used. The use of 24- or 32-bit words leads to unpredictable results. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 7-13 Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) ESSI Programming Model 7.4.1.7 CRA Word-length Control (WL[2:0]) Bits 2119 The WL[2:0] bits are used to select the length of the data words being transferred via the ESSI. Word lengths of 8-, 12-, 16-, 24-, or 32- bits can be selected, as in Table 7-2. The ESSI data path programming model in Figure 7-16 on page 7-31 and Figure 7-17 on page 7-32 has additional information about selecting different length data words. The ESSI data registers are 24 bits long. The ESSI transmits 32-bit words either by duplicating the last bit eight times when WL[2:0] = 100, or by duplicating the first bit eight times when WL[2:0] = 101. The WL[2:0] bits are cleared by a hardware RESET signal or by a software RESET instruction. Table 7-2 ESSI Word Length Selection Freescale Semiconductor, Inc... WL2 0 0 0 0 1 1 1 1 WL1 0 0 1 1 0 0 1 1 WL0 0 1 0 1 0 1 0 1 Number of Bits/Word 8 12 16 24 32 (valid data in the first 24 bits) 32 (valid data in the last 24 bits) Reserved Reserved 7.4.1.8 CRA Select SC1 (SSC1) Bit 22 The SSC1 bit controls the functionality of the SC1 signal. This bit is only valid when the ESSI is configured in synchronous mode (i.e., if the CRB synchronous/asynchronous bit (SYN) is set), and transmitter 2 is disabled (i.e., if transmit enable (TE2) = 0). If SSC1 is set and SC1 is configured as an output (SCD1 = 1), then the SC1 signal acts as the driver enabled signal of transmitter 0. This enables an external buffer for the transmitter 0 output. If SSC1 is cleared, SC1 acts as the serial I/O flag. 7.4.1.9 CRA Reserved Bit 23 This bit is reserved. It is read as 0 and should be written with 0. 7-14 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) ESSI Programming Model 7.4.2 ESSI Control Register B (CRB) The CRB is one of two 24-bit, read/write control registers used to direct the operation of the ESSI; see Figure 7-3 on page 7-9. CRB controls the ESSI multifunction signals, SC[2:0], which can be used as clock inputs or outputs, frame synchronization signals, transmit data signals, or serial I/O flag signals. The serial output flag control bits and the direction control bits for the serial control signals are in the ESSI CRB. Interrupt enable bits for the receiver and the transmitter are also in the CRB. The bit setting of the CRB also determines how many transmitters are enabled (0, 1, 2, or 3 transmitters can be enabled). The CRB settings also determine the ESSI operating mode. Either a hardware RESET signal or a software RESET instruction clears all the bits in the CRB. The relationship between the ESSI signals SC[2:0], SCK, and the CRB bits is summarized in Table 7-4 on page 7-24. The ESSI CRB bits are described in the following paragraphs. 7.4.2.1 CRB Serial Output Flags (OF0, OF1) Bits 0, 1 The ESSI has two serial output flag bits, OF1 and OF0. The normal sequence for setting output flags when transmitting data (by transmitter 0 through the STD signal only) consists of these steps: 1. Wait for TDE (TX0 empty) to be set. 2. Write the flags. 3. Write the transmit data to the TX register. Bits OF0 and OF1 are double-buffered so that the flag states appear on the signals when the TX data is transferred to the transmit shift register. The flag bits values are synchronized with the data transfer. Note: The timing of the optional serial output signals SC[2:0] is controlled by the frame timing and is not affected by the settings of TE2, TE1, TE0, or the receive enable (RE) bit of the CRB. Freescale Semiconductor, Inc... 7.4.2.1.1 CRB Serial Output Flag 0 (OF0) Bit 0 When the ESSI is in synchronous mode and transmitter 1 is disabled (TE1 = 0), the SC0 signal is configured as ESSI flag 0. If the serial control direction bit (SCD0) is set, the SC0 signal is an output. Data present in bit OF0 is written to SC0 at the beginning of the frame in normal mode or at the beginning of the next time slot in network mode. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 7-15 Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) ESSI Programming Model Bit OF0 is cleared by a hardware RESET signal or by a software RESET instruction. 7.4.2.1.2 CRB Serial Output Flag 1 (OF1) Bit 1 When the ESSI is in synchronous mode and transmitter 2 is disabled (TE2 = 0), the SC1 signal is configured as ESSI flag 1. If the serial control direction bit (SCD1) is set, the SC1 signal is an output. Data present in bit OF1 is written to SC1 at the beginning of the frame in normal mode or at the beginning of the next time slot in network mode. Bit OF1 is cleared by a hardware RESET signal or by a software RESET instruction. Freescale Semiconductor, Inc... 7.4.2.2 CRB Serial Control Direction 0 (SCD0) Bit 2 In synchronous mode (SYN = 1) when transmitter 1 is disabled (TE1 = 0), or in asynchronous mode (SYN = 0), SCD0 controls the direction of the SC0 I/O signal. When SCD0 is set, SC0 is an output; when SCD0 is cleared, SC0 is an input. When TE1 is set, the value of SCD0 is ignored, and the SC0 signal is always an output. Bit SCD0 is cleared by a hardware RESET signal or by a software RESET instruction. 7.4.2.3 CRB Serial Control Direction 1 (SCD1) Bit 3 In synchronous mode (SYN = 1) when transmitter 2 is disabled (TE2 = 0), or in asynchronous mode (SYN = 0), SCD1 controls the direction of the SC1 I/O signal. When SCD1 is set, SC1 is an output; when SCD1 is cleared, SC1 is an input. When TE2 is set, the value of SCD1 is ignored, and the SC1 signal is always an output. Bit SCD1 is cleared by a hardware RESET signal or by a software RESET instruction. 7.4.2.4 CRB Serial Control Direction 2 (SCD2) Bit 4 SCD2 controls the direction of the SC2 I/O signal. When SCD2 is set, SC2 is an output; when SCD2 is cleared, SC2 is an input. SCD2 is cleared by a hardware RESET signal or by a software RESET instruction. 7.4.2.5 CRB Clock Source Direction (SCKD) Bit 5 SCKD selects the source of the clock signal. If SCKD is set and the ESSI is in synchronous mode, the internal clock is the source of the clock signal used for all the transmit shift registers and the receive shift register. If SCKD is set and the ESSI is in asynchronous mode, the internal clock source becomes the bit clock for the transmit shift register and word length divider. The internal clock is output on the SCK signal. When SCKD is cleared, the external clock source is selected. The internal clock generator is disconnected from the SCK signal, and an external clock source can drive this signal. Either a hardware RESET signal or a software RESET instruction clears SCKD. 7-16 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) ESSI Programming Model 7.4.2.6 CRB Shift Direction (SHFD) Bit 6 The setting of the SHFD bit determines the shift direction of the transmit or receive shift register. If SHFD is set, data is shifted out with the LSB first. If SHFD is cleared, data is shifted out MSB first; see Figure 7-16 on page 7-31 and Figure 7-17 on page 7-32. Received data is shifted in LSB first when SHFD is set or MSB first when SHFD is cleared. Either a hardware RESET signal or a software RESET instruction clears SHFD. 7.4.2.7 CRB Frame Sync Length FSL[1:0] Bits 7 and 8 These bits select the length of frame sync to be generated or recognized; see Figure 7-11 on page 7-19, Figure 7-14 on page 7-22, and Figure 7-15 on page 7-23. The values of FSL[1:0] are documented in Table 7-3. Table 7-3 FSL1 and FSL0 Encoding Frame Sync Length FSL1 0 0 1 1 FSL0 RX 0 1 0 1 word word bit bit TX word bit bit word Freescale Semiconductor, Inc... The word length is defined by WL[2:0]. Either a hardware RESET signal or a software RESET instruction clears FSL[1:0]. 7.4.2.8 CRB Frame Sync Relative Timing (FSR) Bit 9 The FSR bit determines the relative timing of the receive and transmit frame sync signal in reference to the serial data lines, for word length frame sync only. When FSR is cleared, the word length frame sync occurs together with the first bit of the data word of the first slot. When FSR is set, the word length frame sync occurs one serial clock cycle earlier (i.e., simultaneously with the last bit of the previous data word). Either a hardware RESET signal or a software RESET instruction clears FSR. 7.4.2.9 CRB Frame Sync Polarity (FSP) Bit 10 The FSP bit determines the polarity of the receive and transmit frame sync signals. When FSP is cleared, the frame sync signal polarity is positive (i.e., the frame start is indicated MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 7-17 Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) ESSI Programming Model by the frame sync signal going high). When FSP is set, the frame sync signal polarity is negative (i.e., the frame start is indicated by the frame sync signal going low). Either a hardware RESET signal or a software RESET instruction clears FRB. 7.4.2.10 CRB Clock Polarity (CKP) Bit 11 The CKP bit controls on which bit clock edge data and frame sync are clocked out and latched in. If CKP is cleared, the data and the frame sync are clocked out on the rising edge of the transmit bit clock and latched in on the falling edge of the receive bit clock. If CKP is set, the data and the frame sync are clocked out on the falling edge of the transmit bit clock and latched in on the rising edge of the receive bit clock. Freescale Semiconductor, Inc... Either a hardware RESET signal or a software RESET instruction clears CKP. 7.4.2.11 CRB Synchronous /Asynchronous (SYN) Bit 12 SYN controls whether the receive and transmit functions of the ESSI occur synchronously or asynchronously with respect to each other; see Figure 7-12 on page 7-20. When SYN is cleared, the ESSI is in asynchronous mode, and separate clock and frame sync signals are used for the transmit and receive sections. When SYN is set, the ESSI is in synchronous mode and the transmit and receive sections use common clock and frame sync signals. Only in synchronous mode can more than one transmitter be enabled. Either a hardware RESET signal or a software RESET instruction clears SYN. 7-18 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) ESSI Programming Model Word Length: FSL1 = 0, FSL0 = 0 Serial Clock RX, TX Frame SYNC RX, TX Serial Data Data Data NOTE: Frame sync occurs while data is valid. One Bit Length: FSL1 = 1, FSL0 = 0 Freescale Semiconductor, Inc... Serial Clock RX, TX Frame SYNC RX, TX Serial Data Data Data NOTE: Frame sync occurs for one bit time preceding the data. Mixed Frame Length: FSL1 = 0, FSL0 = 1 Serial Clock RX Frame Sync RXSerial Data TX Frame SYNC TX Serial Data Data Data Data Data Mixed Frame Length: FSL1 = 1, FSL0 = 1 Serial Clock RX Frame SYNC RX Serial Data TX Frame SYNC TX Serial Data Data Data Data Data AA0681 Figure 7-11 CRB FSL0 and FSL1 Bit Operation (FSR = 0) MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 7-19 Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) ESSI Programming Model 7.4.2.12 CRB ESSI Mode Select (MOD) Bit 13 MOD selects the operational mode of the ESSI; see Figure 7-13 on page 7-21, Figure 7-14 on page 7-22, and Figure 7-15 on page 7-23. When MOD is cleared, normal mode is selected; when MOD is set, network mode is selected. In normal mode, the frame rate divider determines the word transfer rate: one word is transferred per frame sync during the frame sync time slot. In network mode, a word can be transferred every time slot. For more details, see Section 7.5NOperating Modes. Either a hardware RESET signal or a software RESET instruction clears MOD. Asynchronous (SYN = 0) Freescale Semiconductor, Inc... Transmitter Frame SYNC STD External Transmit Frame SYNC Internal Frame SYNC External Receive Frame SYNC Clock Frame SYNC SRD RECEIVER NOTE: Transmitter and receiver can have different clocks and frame syncs. SYNCHRONOUS (SYN = 1) Transmitter Frame SYNC STD Clock SC ESSI Bit Clock SC0 External Transmit Clock Internal Clock External Receive Clock SC2 SC1 Clock SCK ESSI Bit Clock External Clock Internal Clock External Frame SYNC Internal Frame SYNC SC2 Clock Frame SYNC SRD Receiver NOTE: Transmitter and receiver can have the same clock frame syncs. AA0682 Figure 7-12 CRB SYN Bit Operation 7-20 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc... Normal Mode (MOD = 0) Serial Clock SSI Control Register B (CRB) (READ/WRITE) MOTOROLA Transmitter Interrupt (or DMA Request) and Flags Set Data Receiver Interrupt (or DMA Request) and Flags Set Data Network Mode (MOD = 1) Transmitter Interrupts (or DMA Request) and Flags Set Slot 1 Slot 2 Slot 3 Slot 1 Slot 2 Receiver Interrupt (or DMA Request) and Flags Set AA0683 Frame SYNC Serial Data NOTE: Interrupts occur and data is transferred once per frame sync. Serial Clock Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com DSP56309UM/D Figure 7-13 CRB MOD Bit Operation Frame SYNC Serial Data NOTE: Interrupts occur every time slot and a word may be transferred. Enhanced Synchronous Serial Interface (ESSI) ESSI Programming Model 7-21 Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) ESSI Programming Model Frame SYNC (FSL0 = 0, FSL1 = 0) Frame SYNC (FSL0 = 0, FSL1 = 1) Data Out Flags Freescale Semiconductor, Inc... Slot 0 Wait Slot 0 AA0684 Figure 7-14 Normal Mode, External Frame Sync (8 Bit, 1 Word in Frame) 7.4.2.13 Enabling, Disabling ESSI Data Transmission The ESSI has three transmit enable bits (TE[2:0]), one for each data transmitter. The process of transmitting data from TX1 and TX2 is the same. TX0 can also operate in asynchronous mode. The normal transmit enable sequence is to write data to one or more transmit data registers (or the time slot register (TSR)) before setting the TE bit. The normal transmit disable sequence is to clear the TE, transmit interrupt enable (TIE), and transmit exception interrupt enable (TEIE) bits after the transmit data empty (TDE) bit is set. In network mode, clearing the appropriate TE bit and setting it again disables the corresponding transmitter (0, 1, or 2) after transmission of the current data word. The transmitter remains disabled until the beginning of the next frame. During that time period, the corresponding SC (or STD in the case of TX0) signal remains in the high-impedance state. 7.4.2.14 CRB ESSI Transmit 2 Enable (TE2) Bit 14 The TE2 bit enables the transfer of data from TX2 to transmit shift register 2. TE2 is functional only when the ESSI is in synchronous mode and is ignored when the ESSI is in asynchronous mode. When TE2 is set and a frame sync is detected, transmitter 2 is enabled for that frame. When TE2 is cleared, transmitter 2 is disabled after completing transmission of data currently in the ESSI transmit shift register. Any data present in TX2 is not transmitted. If TE2 is cleared, data can be written to TX2; the TDE bit is cleared, but data is not transferred to transmit shift register 2. 7-22 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) ESSI Programming Model Keeping the TE2 bit cleared until the start of the next frame causes the SC1 signal to act as serial I/O flag from the start of the frame, in both normal and network mode. The on-demand mode transmit enable sequence can be the same as normal mode, or the TE2 bit can be left enabled. The TE2 bit is cleared by either a hardware RESET signal or a software RESET instruction. Note: The setting of the TE2 bit does not affect the generation of frame sync or output flags. Freescale Semiconductor, Inc... Frame SYNC (FSL0 = 0, FSL1 = 0) Frame SYNC (FSL0 = 0, FSL1 = 1) Data Flags SLOT 0 SLOT 1 SLOT 0 SLOT 1 AA1593 Figure 7-15 Network Mode, External Frame Sync (8 Bit, 2 Words in Frame) 7.4.2.15 CRB ESSI Transmit 1 Enable (TE1) Bit 15 The TE1 bit enables the transfer of data from TX1 to transmit shift register 1. TE1 is functional only when the ESSI is in synchronous mode and is ignored when the ESSI is in asynchronous mode. When TE1 is set and a frame sync is detected, the transmitter 1 is enabled for that frame. When TE1 is cleared, transmitter 1 is disabled after completing transmission of data currently in the ESSI transmit shift register. Any data present in TX1 is not transmitted. If TE1 is cleared, data can be written to TX1; the TDE bit is cleared, but data is not transferred to transmit shift register 1. Keeping the TE1 bit cleared until the start of the next frame causes the SC0 signal to act as serial I/O flag from the start of the frame, in both normal and network mode. The transmit enable sequence for on-demand mode can be the same as for normal mode, or the TE1 bit can be left enabled. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 7-23 Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) ESSI Programming Model The TE1 bit is cleared by either a hardware RESET signal or a software RESET instruction. Note: The setting of the TE1 bit does not affect the generation of frame sync or output flags. 7.4.2.16 CRB ESSI Transmit 0 Enable (TE0) Bit 16 The TE0 bit enables the transfer of data from TX0 to transmit shift register 0. TE0 is functional when the ESSI is in either synchronous or asynchronous mode. When TE0 is set and a frame sync is detected, the transmitter 0 is enabled for that frame. Freescale Semiconductor, Inc... When TE0 is cleared, transmitter 0 is disabled after completing transmission of data currently in the ESSI transmit shift register. The STD output is tri-stated, and any data present in TX0 is not transmitted (i.e., data can be written to TX0 with TE0 cleared; the TDE bit is cleared, but data is not transferred to the transmit shift register 0). The TE0 bit is cleared by either a hardware RESET signal or a software RESET instruction. The transmit enable sequence for on-demand mode can be the same as for normal mode, or TE0 can be left enabled. Note: Transmitter 0 is the only transmitter that can operate in asynchronous mode (SYN = 0). TE0 does not affect the generation of frame sync or output flags. Table 7-4 summarizes the preceding sections; it shows possible settings of control bits and their associated signals. Table 7-4 Mode and Signal Definition Table Control Bits SYN 0 0 0 0 1 TE0 0 0 1 1 0 TE1 X X X X 0 TE2 X X X X 0 RE 0 1 0 1 0 SC0 U RXC U RXC U SC1 U FSR U FSR U ESSI Signals SC2 U U FST FST U SCK U U TXC TXC U STD U U TD0 TD0 U SRD U RD U RD U 7-24 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) ESSI Programming Model Table 7-4 Mode and Signal Definition Table (Continued) Control Bits SYN 1 1 1 TE0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 TXC RXC XC FST FSR FS TD0 TD1 TD2 T0D RD F0 F1 U X = = = = = = = = = = = = = = = ESSI Signals RE 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SC0 F0/U F0/U F0/U TD1 TD1 TD1 TD1 F0/U F0/U F0/U F0/U TD1 TD1 TD1 TD1 SC1 F1/T0D/U TD2 TD2 F1/T0D/U F1/T0D/U TD2 TD2 F1/T0D/U F1/T0D/U TD2 TD2 F1/T0D/U F1/T0D/U TD2 TD2 SC2 FS FS FS FS FS FS FS FS FS FS FS FS FS FS FS SCK XC XC XC XC XC XC XC XC XC XC XC XC XC XC XC STD U U U U U U U TD0 TD0 TD0 TD0 TD0 TD0 TD0 TD0 SRD RD U RD U RD U RD U RD U RD U RD U RD TE1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 TE2 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Freescale Semiconductor, Inc... 1 1 1 1 1 1 1 1 1 1 1 1 Note: Note: Note: Note: Note: Note: Note: Note: Note: Note: Note: Note: Note: Note: Note: Transmitter Clock Receiver Clock Transmitter/Receiver Clock (Synchronous Operation) Transmitter Frame Sync Receiver Frame Sync Transmitter/Receiver Frame Sync (Synchronous Operation) Transmit Data signal 0 Transmit Data signal 1 Transmit Data signal 2 Transmitter 0 drive enable if SSC1 = 1 & SCD1 = 1 Receive Data Flag 0 Flag 1 if SSC1 = 0 Unused (can be used as GPIO signal) Indeterminate MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 7-25 Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) ESSI Programming Model 7.4.2.17 CRB ESSI Receive Enable (RE) Bit 17 When the RE bit is set, the receive portion of the ESSI is enabled. When this bit is cleared, the receiver is disabled by inhibiting data transfer into RX. If data is being received while this bit is cleared, the remainder of the word is shifted in and transferred to the ESSI receive data register. RE must be set in both the normal and on-demand modes for the ESSI to receive data. In network mode, clearing RE and setting it again disables the receiver after reception of the current data word. The receiver remains disabled until the beginning of the next data frame. Freescale Semiconductor, Inc... RE is cleared by either a hardware RESET signal or a software RESET instruction. Note: The setting of the RE bit does not affect the generation of a frame sync. 7.4.2.18 CRB ESSI Transmit Interrupt Enable (TIE) Bit 18 Setting the TIE bit enables a DSP transmit interrupt, which is generated when both the TIE and the TDE bits in the ESSI status register are set. When TIE is cleared, the transmit interrupt is disabled. The use of the transmit interrupt is described in Section 7.5.3. Writing data to the data registers of the enabled transmitters or to the TSR clears TDE and also clears the interrupt. Transmit interrupts with exception conditions have higher priority than normal transmit data interrupts. If the transmitter underrun error (TUE) bit is set, signaling that an exception has occurred, and the TEIE bit is set, the ESSI requests an SSI transmit data with exception interrupt from the interrupt controller. TIE is cleared by either a hardware RESET signal or a software RESET instruction. 7.4.2.19 CRB ESSI Receive Interrupt Enable (RIE) Bit 19 Setting the RIE enables a DSP receive data interrupt, which is generated when both the RIE and receive data register full (RDF) bit in the SSISR are set. When RIE is cleared, this interrupt is disabled. The use of the receive interrupt is described in Section 7.5.3. Reading the receive data register clears RDF and the pending interrupt. Receive interrupts with exception have higher priority than normal receive data interrupts. If the receiver overrun error (ROE) bit is set, signaling that an exception has occurred, and the REIE bit is set, the ESSI requests an SSI receive data with exception interrupt from the interrupt controller. RIE is cleared by either a hardware RESET signal or a software RESET instruction. 7.4.2.20 Transmit Last Slot Interrupt Enable (TLIE) Bit 20 Setting the TLIE bit enables an interrupt at the beginning of the last slot of a frame when the ESSI is in network mode. When TLIE is set, the DSP is interrupted at the start of the last slot in a frame regardless of the transmit mask register setting. When TLIE is cleared, 7-26 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) ESSI Programming Model the transmit last slot interrupt is disabled. The use of the transmit last slot interrupt is described in Section 7.5.3NESSI Exceptions. TLIE is cleared by either a hardware RESET signal or a software RESET instruction. TLIE is disabled when the ESSI is in on-demand mode (DC = $0). 7.4.2.21 Receive Last Slot Interrupt Enable (RLIE) Bit 21 Setting the RLIE bit enables an interrupt after the last slot of a frame ends when the ESSI is in network mode. When RLIE is set, the DSP is interrupted after the last slot in a frame ends regardless of the receive mask register setting. When RLIE is cleared, the receive last slot interrupt is disabled. The use of the receive last slot interrupt is described in Section 7.5.3NESSI Exceptions. RLIE is cleared by either a hardware RESET signal or a software RESET instruction. RLIE is disabled when the ESSI is in on-demand mode (DC = $0). 7.4.2.22 Transmit Exception Interrupt Enable (TEIE) Bit 22 When the TEIE bit is set, the DSP is interrupted when both TDE and TUE in the ESSI Status Register are set. When TEIE is cleared, this interrupt is disabled. The use of the transmit interrupt is described in Section 7.5.3NESSI Exceptions. Reading the status register, followed by writing to all the data registers of the enabled transmitters, clears both TUE and the pending interrupt. TEIE is cleared by either a hardware RESET signal or a software RESET instruction. 7.4.2.23 Receive Exception Interrupt Enable (REIE) Bit 23 When the REIE bit is set, the DSP is interrupted when both RDF and ROE in the ESSI status register are set. When REIE is cleared, this interrupt is disabled. The use of the receive interrupt is described in Section 7.5.3NESSI Exceptions. Reading the status register followed by reading the receive data register clears both ROE and the pending interrupt. REIE is cleared by either a hardware RESET signal or a software RESET instruction. Freescale Semiconductor, Inc... 7.4.3 ESSI Status Register (SSISR) The SSISR (in Figure 7-4 on page 7-9) is a 24-bit, read-only status register used by the DSP to read the status and serial input flags of the ESSI. The SSISR bits are documented in the following paragraphs. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 7-27 Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) ESSI Programming Model 7.4.3.1 SSISR Serial Input Flag 0 (IF0) Bit 0 The IF0 bit is enabled only when SC0 is an input flag and synchronous mode is selected (i.e., when the SYN bit is set, and the TE1 and SCD0 bits are cleared). The ESSI latches data present on the SC0 signal during reception of the first received bit after the frame sync is detected. The IF0 bit is updated with this data when the data in the receive shift register is transferred into the receive data register. If it is not enabled, the IF0 bit is cleared. Freescale Semiconductor, Inc... A hardware RESET signal, software RESET instruction, ESSI individual reset, or STOP instruction clears the IF0 bit. 7.4.3.2 SSISR Serial Input Flag 1 (IF1) Bit 1 The IF1 bit is enabled only when SC1 is an input flag and synchronous mode is selected, the SYN bit is set, and the TE2 and SCD1 bits are cleared. The ESSI latches data present on the SC1 signal during reception of the first received bit after the frame sync is detected. The IF1 bit is updated with this data when the data in the receive shift register is transferred into the receive data register. If it is not enabled, the IF1 bit is cleared. A hardware RESET signal, software RESET instruction, ESSI individual reset, or STOP instruction clears the IF1 bit. 7.4.3.3 SSISR Transmit Frame Sync Flag (TFS) Bit 2 When set, TFS indicates that a transmit frame sync occurred in the current time slot. TFS is set at the start of the first time slot in the frame and cleared during all other time slots. If the transmitter is enabled, data written to a transmit data register during the time slot when TFS is set is transmitted (in network mode) during the second time slot in the frame. TFS is useful in network mode to identify the start of a frame. TFS is valid only if at least one transmitter is enabled (TE0, TE1 or TE2 are set). A hardware RESET signal, software RESET instruction, ESSI individual reset, or STOP instruction clears TFS. Note: In normal mode, TFS is always read as 1 when transmitting data because there is only one time slot per frame, the Oframe syncO time slot. 7.4.3.4 SSISR Receive Frame Sync Flag (RFS) Bit 3 When set, the RFS bit indicates that a receive frame sync occurred during the reception of a word in the serial receive data register. This means that the data word is from the 7-28 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) ESSI Programming Model first time slot in the frame. When the RFS bit is cleared and a word is received, it indicates (only in Network mode) that the frame sync did not occur during reception of that word. RFS is valid only if the receiver is enabled (i.e., the RE bit is set). A hardware RESET signal, software RESET instruction, ESSI individual reset, or STOP instruction clears RFS. Note: In normal mode, RFS is always read as 1 when reading data because there is only one time slot per frame, the frame sync time slot. Freescale Semiconductor, Inc... 7.4.3.5 SSISR Transmitter Underrun Error Flag (TUE) Bit 4 The TUE bit is set when at least one of the enabled serial transmit shift registers is empty (no new data to be transmitted) and a transmit time slot occurs. When a transmit underrun error occurs, the previous data (which is still present in the TX registers that were not written) is retransmitted. In normal mode, there is only one transmit time slot per frame. In network mode, there can be up to thirty-two transmit time slots per frame. If the TEIE bit is set, a DSP transmit underrun error interrupt request is issued when the TUE bit is set. A hardware RESET signal, software RESET instruction, ESSI individual reset, or STOP instruction clears TUE. TUE can also be cleared by first reading the SSISR with the TUE bit set, then writing to all the enabled transmit data registers or to the TSR. 7.4.3.6 SSISR Receiver Overrun Error Flag (ROE) Bit 5 The ROE bit is set when the serial receive shift register is filled and ready to transfer to the receive data register (RX), but RX is already full (i.e., the RDF bit is set). If the REIE bit is set, a DSP receiver overrun error interrupt request is issued when the ROE bit is set. A hardware RESET signal, software RESET instruction, ESSI individual reset, or STOP instruction clears ROE. ROE can also be cleared by reading the SSISR with the ROE bit set and then reading the RX. 7.4.3.7 ESSI Transmit Data Register Empty (TDE) Bit 6 The TDE bit is set when the contents of the transmit data register of every enabled transmitter are transferred to the transmit shift register. It is also set for a TSR disabled time slot period in network mode (as if data were being transmitted after the TSR was written). When set, the TDE bit indicates that data should be written to all the TX registers of the enabled transmitters or to the TSR. The TDE bit is cleared when the DSP56309 writes to all the transmit data registers of the enabled transmitters or when the DSP writes to the TSR to disable transmission of the next time slot. If the TIE bit is set, a DSP transmit data interrupt request is issued when TDE is set. A hardware RESET signal, software RESET instruction, ESSI individual reset, or STOP instruction clears the TDE bit. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 7-29 Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) ESSI Programming Model 7.4.3.8 ESSI Receive Data Register Full (RDF) Bit 7 The RDF bit is set when the contents of the receive shift register are transferred to the receive data register. The RDF bit is cleared when the DSP reads the receive data register. If RIE is set, a DSP receive data interrupt request is issued when RDF is set. A hardware RESET signal, software RESET instruction, ESSI individual reset, or STOP instruction clears the RDF bit. The ESSI data path programming models are shown in Figure 7-16 on page 7-31 and Figure 7-17 on page 7-32. Freescale Semiconductor, Inc... 7-30 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) ESSI Programming Model 23 Receive High Byte 7 Serial 23 Receive Receive High Byte Shift Register 7 16 15 Receive Middle Byte 0 7 87 Receive Low Byte 07 87 Receive Middle Byte Receive Low Byte 07 0 ESSI Receive Data Register (Read Only) 0 0 16 15 0 7 0 24 Bit Freescale Semiconductor, Inc... 16 Bit 12 Bit 8 Bit WL1, WL0 MSB 8-bit Data MSB MSB 16-bit Data MSB 24-bit Data (a) Receive Registers NOTES: Data is received MSB first if SHFD = 0. 24-bit fractional format (ALC = 0). 32-bit mode is not shown. 16 15 Transmit High Byte 7 23 STD 7 MSB MSB MSB MSB (b) Transmit Registers 8-bit Data 12-bit Data 16-bit Data LSB 24-bit Data NOTES: Data is transmitted MSB first if SHFD = 0. 4-bit fractional format (ALC = 0). 32-bit mode is not shown. Transmit High Byte 0 LSB 0 LSB LSB 0 0 7 0 7 Transmit Middle Byte 07 07 Transmit Middle Byte 07 Transmit Low Byte 0 Least Significant Zero Fill 87 Transmit Low Byte 0 0 ESSI Transmit Shift Register 0 LSB 12-bit Data LSB 0 LSB LSB 0 0 SRD Least Significant Zero Fill 23 ESSI Transmit Data Register (Write Only) 16 15 AA0686 Figure 7-16 ESSI Data Path Programming Model (SHFD = 0) MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 7-31 Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) ESSI Programming Model 23 Receive High Byte 7 23 SRD 7 MSB 8-bit Data MSB Receive High Byte 16 15 Receive Middle Byte 0 7 87 Receive Low Byte 07 07 Receive Middle Byte Receive Low Byte 07 0 LSB LSB 0 0 0 ESSI Receive Data Register (Read Only) 0 0 ESSI Receive Shift Register 0 Least Significant Zero Fill 16 15 0 LSB 7 Freescale Semiconductor, Inc... 12-bit Data MSB 16-bit Data MSB LSB 24-bit Data NOTES: Data is received MSB first if SHFD = 0. 24-bit fractional format (ALC = 0). 32-bit mode is not shown. 0 ESSI Transmit Data Register Transmit Low Byte (Write Only) 0 0 Transmit Low Byte 07 0 ESSI Transmit Shift Register 24 Bit (a) Receive Registers 23 Transmit High Byte 7 23 Transmit High Byte 7 16 15 Transmit Middle Byte 0 7 87 07 07 Transmit Middle Byte 16 15 0 7 16 Bit 12 Bit 8 Bit STD MSB 8-bit Data MSB LSB 0 LSB LSB 16-bit Data LSB 24-bit Data NOTES: Data is received MSB first if SHFD = 0. 4-bit fractional format (ALC = 0). 32-bit mode is not shown. AA0687 0 0 WL1, WL0 Least Significant Zero Fill 12-bit Data MSB MSB (b) Transmit Registers Figure 7-17 ESSI Data Path Programming Model (SHFD = 1) 7-32 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) ESSI Programming Model 7.4.4 ESSI Receive Shift Register The 24-bit receive shift register (in Figure 7-16 on page 7-31 and Figure 7-17 on page 7-32) receives the incoming data from the serial receive data signal. Data is shifted in by the selected (internal/external) bit clock when the associated frame sync I/O is asserted. It is assumed that data is received MSB first if SHFD is cleared and LSB first if SHFD is set. Data is transferred to the ESSI receive data register after 8, 12, 16, 24, or 32 serial clock cycles are counted, depending on the word-length control bits in the CRA. Freescale Semiconductor, Inc... 7.4.5 ESSI Receive Data Register (RX) The receive data register (RX) is a 24-bit, read-only register that accepts data from the receive shift register as it becomes full; see Figure 7-16 on page 7-31 and Figure 7-17 on page 7-32. The data read is aligned according to the value of the ALC bit. When the ALC bit is cleared, the MSB is bit 23 and the least significant byte is unused. When the ALC bit is set, the MSB is bit 15 and the most significant byte is unused. Unused bits are read as 0s. If the associated interrupt is enabled, the DSP is interrupted whenever the RX register becomes full. 7.4.6 ESSI Transmit Shift Registers The three 24-bit transmit shift registers contain the data being transmitted; see Figure 7-16 on page 7-31 and Figure 7-17 on page 7-32. Data is shifted out to the serial transmit data signals by the selected (internal/external) bit clock when the associated frame sync I/O is asserted. The word-length control bits in the CRA determine the number of bits that must be shifted out before the shift registers are considered empty and can be written to again. Depending on the setting of the CRA, the number of bits to be shifted out can be 8, 12, 16, 24, or 32 bits. The data transmitted is aligned according to the value of the ALC bit. When the ALC bit is cleared, the MSB is bit 23 and the least significant byte is unused. When ALC is set, the MSB is bit 15 and the most significant byte is unused. Unused bits are read as 0s. Data is shifted out of these registers MSB first if the SHFD bit is cleared and LSB first if the SHFD bit is set. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 7-33 Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) ESSI Programming Model 7.4.7 ESSI Transmit Data Registers (TX0-2) TX20, TX10, and TX00 are transmit data registers for ESSI0. TX21, TX11, and TX01 are transmit data registers for ESSI1. TX20 and TX21 are known as TX2. TX10 and TX11 are known as TX1. TX00 and TX01 are known as TX0. TX2, TX1, and TX0 are 24-bit, write-only registers. Data to be transmitted is written into these registers and automatically transferred to the transmit shift registers; see Figure 7-16 on page 7-31 and Figure 7-17 on page 7-32. The data transmitted (8, 12, 16, or 24 bits) is aligned according to the value of the ALC bit. When the ALC bit is cleared, the MSB is Bit 23. When ALC is set, the MSB is Bit 15. If the transmit data register empty interrupt has been enabled, the DSP is interrupted whenever a transmit data register becomes empty. Note: When data is written to a peripheral device, there is a two cycle pipeline delay until any status bits affected by this operation are updated. If you read any of those status bits within the next two cycles, the bit does not reflect its current status. See the DSP56300 Family Manual, Appendix B, Polling a Peripheral Device for Write for further details. Freescale Semiconductor, Inc... 7.4.8 ESSI Time Slot Register (TSR) TSR is effectively a write-only null data register that is used to prevent data transmission in the current transmit time slot. For the purposes of timing, TSR is a write-only register that behaves like an alternative transmit data register, except that, rather than transmitting data, the transmit data signals of all the enabled transmitters are in the high-impedance state for the current time slot. 7.4.9 Transmit Slot Mask Registers (TSMA, TSMB) The transmit slot mask Registers are two 16-bit, read/write registers. When the TSMA or TSMB is read to the internal data bus, the register contents occupy the two low-order bytes of the data bus, and the high-order byte is zero-filled. In network mode, these registers are used by the transmitter(s) to determine what action to take in the current transmission slot. Depending on the setting of the bits, the transmitter(s) either tri-state the transmitter(s) data signal(s) or transmit a data word and generate a transmitter empty condition. 7-34 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) ESSI Programming Model TSMA and TSMB (in Figure 7-16 on page 7-31 and Figure 7-17 on page 7-32) can be seen as a single 32-bit register, TSM. Bit n in TSM (TSn) is an enable/disable control bit for transmission in slot number N. When TSn is cleared, all the transmit data signals of the enabled transmitters are tri-stated during transmit time slot number N. The data is still transferred from the enabled transmit data register(s) to the transmit shift register. However, the TDE and the TUE flags are not set. This means that during a disabled slot, no transmitter empty interrupt is generated. The DSP is interrupted only for enabled slots. Data written to the transmit data register when servicing the transmitter empty interrupt request is transmitted in the next enabled transmit time slot. Freescale Semiconductor, Inc... When TSn is set, the transmit sequence proceeds normally. Data is transferred from the TX register to the shift register during slot number N and the TDE flag is set. Using the TSM slot mask does not conflict with using the TSR. Even if a slot is enabled in the TSM, you can write to the TSR to tri-state the signals of the enabled transmitters during the next transmission slot. Setting the bits in the TSM affects the next frame transmission. The frame currently being transmitted is not affected by the new TSM setting. If the TSM is read, it shows the current setting. After a hardware RESET signal or software RESET instruction, the TSM register is reset to $FFFFFFFF; this setting enables all thirty-two slots for data transmission. 7.4.10 Receive Slot Mask Registers (RSMA, RSMB) The receive slot mask registers are two 16-bit, read/write registers. In network mode, these registers are used by the receiver(s) to determine what action to take in the current time slot. Depending on the setting of the bits, the receiver(s) either tri-state the receiver(s) data signal(s) or receive a data word and generate a receiver full condition. RSMA and RSMB (in Figure 7-16 on page 7-31 and Figure 7-17 on page 7-32) can be seen as one 32-bit register, RSM. Bit n in RSM (RSn) is an enable/disable control bit for time slot number N. When RSn is cleared, all the data signals of the enabled receivers are tri-stated during time slot number N. Data is transferred from the receive data register(s) to the receive shift register(s) and the RDF and ROE flags are not set. During a disabled slot, no receiver full interrupt is generated. The DSP is interrupted only for enabled slots. When RSn is set, the receive sequence proceeds normally. Data is received during slot number N, and the RDF flag is set. Setting the bits in the RSM affects the next frame transmission. The frame currently being transmitted is not affected by the new RSM setting. If the RSM is read, it shows the current setting. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 7-35 Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) Operating Modes When the RSMA or RSMB register are read by the internal data bus, the register contents occupy the two low-order bytes of the data bus, and the high-order byte is zero-filled. After a hardware RESET signal or a software RESET instruction, the RSM register is reset to $FFFFFFFF; this setting enables all thirty-two time slots for data transmission. 7.5 OPERATING MODES Freescale Semiconductor, Inc... The ESSI operating modes are selected by the ESSI control registers (CRA and CRB). The operating modes are described in the following paragraphs. 7.5.1 ESSI After Reset A hardware RESET signal or software RESET instruction clears the port control register and the port direction control register. This situation configures all the ESSI signals as GPIO. The ESSI is in the reset state while all ESSI signals are programmed as GPIO; the ESSI is active only if at least one of the ESSI I/O signals is programmed as an ESSI signal. 7.5.2 ESSI Initialization To initialize the ESSI, do the following: 1. Send a reset: a hardware RESET signal, software RESET instruction, ESSI individual reset, or STOP instruction. 2. Program the ESSI control and time slot registers. 3. Write data to all the enabled transmitters. 4. Configure at least one signal as an ESSI signal. 5. If an external frame sync is used, from the moment the ESSI is activated, at least five serial clocks are needed before the first external frame sync is supplied. Otherwise, improper operation can result. Clearing the PC[5:0] bits in the GPIO PCR during program execution causes the ESSI to stop serial activity and enter the individual reset state. All status bits of the interface are set to their reset state. The contents of CRA and CRB are not affected. The ESSI individual reset allows a program to reset each interface separately from the other 7-36 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) Operating Modes internal peripherals. During ESSI individual reset, internal DMA accesses to the data registers of the ESSI are not valid and data read is undefined. To insure proper operation of the ESSI, use an ESSI individual reset when changing the ESSI control registers (except for bits TEIE, REIE, TLIE, RLIE, TIE, RIE, TE2, TE1, TE0, and RE). Here is an example of initializing the ESSI. 1. Put the ESSI in its individual reset state by clearing the PCR bits. Freescale Semiconductor, Inc... 2. Configure the control registers (CRA, CRB) to set the operating mode. Disable the transmitters and receiver by clearing the TE[2:0] and RE bits. Set the interrupt enable bits for the operating mode chosen. 3. Enable the ESSI by setting the PCR bits to activate the input/output signals to be used. 4. Write initial data to the transmitters that are used during operation. This step is needed even if DMA is used to service the transmitters. 5. Enable the transmitters and receiver to be used. Now the ESSI can be serviced by polling, interrupts, or DMA. Once the ESSI has been enabled (Step 3), operation starts as follows: For internally generated clock and frame sync, these signals start activity immediately after the ESSI is enabled. Data is received by the ESSI after the occurrence of a frame sync signal (either internally or externally generated) only when the receive enable (RE) bit is set. Data is transmitted after the occurrence of a frame sync signal (either internally or externally generated) only when the transmitter enable (TE[2:0]) bit is set. 7.5.3 ESSI Exceptions The ESSI can generate six different exceptions. They are discussed in the following paragraphs (ordered from the highest to the lowest exception priority): 1. ESSI receive data with exception status: Occurs when the receive exception interrupt is enabled, the receive data register is full, and a receiver overrun error has occurred. This exception sets the ROE bit. The ROE bit is cleared by first reading the SSISR and then reading RX. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 7-37 Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) Operating Modes 2. ESSI receive data: Occurs when the receive interrupt is enabled, the receive data register is full, and no receive error conditions exist. Reading RX clears the pending interrupt. This error-free interrupt can use a fast interrupt service routine for minimum overhead. 3. ESSI receive last slot interrupt: Occurs when the ESSI is in network mode and the last slot of the frame has ended. This interrupt is generated regardless of the receive mask register setting. The receive last slot interrupt can be used to signal that the receive mask slot register can be reset, the DMA channels can be reconfigured, and data memory pointers can be reassigned. Using the receive last slot interrupt guarantees that the previous frame was serviced with the previous setting and the new frame is serviced with the new setting without synchronization problems. Note: The maximum time it takes to service a receive last slot interrupt should not exceed N 1 ESSI bits service time (where N is the number of bits the ESSI can transmit per time slot). Freescale Semiconductor, Inc... 4. ESSI transmit data with exception status: Occurs when the transmit exception interrupt is enabled, at least one transmit data register of the enabled transmitters is empty, and a transmitter underrun error has occurred. This exception sets the TUE bit. The TUE bit is cleared by first reading the SSISR and then writing to all the transmit data registers of the enabled transmitters or by writing to the TSR to clear the pending interrupt. 5. ESSI transmit last slot interrupt: Occurs when the ESSI is in network mode at the start of the last slot of the frame. This exception occurs regardless of the transmit mask register setting. The transmit last slot interrupt can be used to signal that the transmit mask slot register can be reset, the DMA channels can be reconfigured, and data memory pointers can be reassigned. Using the transmit last slot interrupt guarantees that the previous frame was serviced with the previous setting, and the new frame is serviced with the new setting without synchronization problems. Note: The maximum transmit last slot interrupt service time should not exceed N 1 ESSI bits service time (where N is the number of bits in a slot). 6. ESSI transmit data: Occurs when the transmit interrupt is enabled, at least one of the enabled transmit data registers is empty, and no transmitter error conditions exist. Writing to all the enabled TX registers or to the TSR clears this interrupt. This error-free interrupt can use a fast interrupt service routine for minimum overhead (if no more than two transmitters are used). To configure an ESSI exception, perform the following steps: 7-38 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) Operating Modes 1. Configure interrupt service routine (ISR) a. Load vector base address register. VBA (b23:8) b. Define I_VEC to be equal to the VBA value (if that is nonzero). If it is defined, I_VEC must be defined for the assembler before the interrupt equate file is included. c. Load the exception vector table entry: two-word fast interrupt or jump/branch to subroutine (long interrupt). p:I_SI0TD 2. Configure interrupt trigger/preload transmit data a. Enable and prioritize overall peripheral interrupt functionality. IPRP (S0L1:0) b. Enable peripheral and associated signals. c. Write data to all enabled transmit registers. d. Enable peripheral interrupt-generating function. e. Enable specific peripheral interrupt. f. Unmask interrupts at global level. Notes: PCRC (PC5:0) TX00 CRB (TE0) CRB0 (TIE) SR (I1:0) Freescale Semiconductor, Inc... 1. The example material to the right of the steps above shows register settings for configuring an ESSI0 transmit interrupt using transmitter 0. 2. The order of the steps is optional except that the interrupt trigger configuration must not be completed until the ISR configuration has been completed. Since 2d can cause an immediate transmit without generating an interrupt, perform the transmit data preload in 2c before 2d to insure valid data is sent in the first transmission. 3. After the first transmit, subsequent transmit values are typically loaded into TXnn by the ISR (one value per register per interrupt). Therefore, if N items are to be sent from a particular TXnn, the ISR will need to load the transmit register (N 1) times. 4. Steps d and e can be performed using a single instruction. 5. If an interrupt trigger event occurs at a time when not all interrupt trigger configuration steps have been performed, the event is ignored forever (the event is not queued in this case). 6. If interrupts derived from the core or other peripherals need to be enabled at the same time as ESSI interrupts, step f should be done last. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 7-39 Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) Operating Modes 7.5.4 Operating Modes: Normal, Network, and On-Demand The ESSI has three basic operating modes and several data/operation formats. These modes can be programmed using the ESSI control registers. The data/operation formats available to the ESSI are selected by setting or clearing control bits in the CRA and CRB. These control bits are WL[2:1], MOD, SYN, FSL[1:0], FSR, FSP, CKP, and SHFD. 7.5.4.1 Normal/Network/On-Demand Mode Selection To select normal mode (or network mode), clear (or set) the MOD bit in the CRB. In normal mode, the ESSI sends or receives one data word per frame (per enabled receiver or transmitter). In network mode, two to thirty-two time slots per frame can be selected. During each frame, zero to thirty-two data words can be received or transmitted (from each enabled receiver or transmitter). In either case, the transfers are periodic. Normal mode is typically used to transfer data to or from a single device. Network mode is typically used in TDM networks of codecs or DSPs with multiple words per frame. Network mode has a sub-mode called on-demand mode. Setting the MOD bit in the CRB for network mode, and setting the frame rate divider to 0 (DC = $00000) selects the on-demand mode. This sub-mode does not generate a periodic frame sync. A frame sync pulse is generated only when data is available to transmit. The frame sync signal indicates the first time slot in the frame. The on-demand mode requires that the transmit frame sync be internal (output) and the receive frame sync be external (input). For simplex operation, synchronous mode could be used; however, for full-duplex operation, asynchronous mode must be used. Data transmission that is data driven is enabled by writing data into each TX. Although the ESSI is double-buffered, only one word can be written to each TX, even if the transmit shift register is empty. The receive and transmit interrupts function normally, using TDE and RDF; however, transmit underruns are impossible for Oon- demandO transmission and are disabled. This mode is useful for interfacing to codecs requiring a continuous clock. 7.5.4.2 Synchronous/Asynchronous Operating Modes The transmit and receive sections of the ESSI interface can be synchronous or asynchronous. The transmitter and receiver use common clock and synchronization signals in synchronous mode; they use separate clock and sync signals in asynchronous mode. The SYN bit in CRB selects synchronous or asynchronous operation. When the SYN bit is cleared, the ESSI TX and RX clocks and frame sync sources are independent. If the SYN bit is set, the ESSI TX and RX clocks and frame sync are driven by the same source (either external or internal). Since the ESSI is designed to operate either synchronously or asynchronously, separate receive and transmit interrupts are provided. Freescale Semiconductor, Inc... 7-40 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) Operating Modes Transmitter 1 and transmitter 2 operate only in synchronous mode. Data clock and frame sync signals can be generated internally by the DSP or can be obtained from external sources. If clocks are internally generated, the ESSI clock generator derives bit clock and frame sync signals from the DSP internal system clock. The ESSI clock generator consists of a selectable fixed prescaler with a programmable prescaler for bit rate clock generation and a programmable frame-rate divider with a word-length divider for frame-rate sync-signal generation. 7.5.4.3 Frame Sync Selection The transmitter and receiver can operate independently. The transmitter can have either a bit-long or word-long frame-sync signal format, and the receiver can have the same or another format. The selection is made by programming FSL[1:0], FSR, and FSP bits in the CRB. 7.5.4.3.1 Frame Sync Signal Format FSL1 controls the frame-sync signal format. If the FSL1 bit is cleared, the RX frame sync is asserted during the entire data transfer period. This frame sync length is compatible with Motorola codecs, serial peripherals that conform to the Motorola SPI, serial A/D and D/A converters, shift registers, and telecommunication pulse code modulation (PCM) serial I/O. If the FSL1 bit is set, the RX frame sync pulses active for one bit clock immediately before the data transfer period. This frame sync length is compatible with Intel and National components, codecs, and telecommunication PCM serial I/O. 7.5.4.3.2 Frame Sync Length for Multiple Devices The ability to mix frame sync lengths is useful in configuring systems in which data is received from one type of device (e.g., codec) and transmitted to a different type of device. FSL0 controls whether RX and TX have the same frame sync length. If the FSL0 bit is cleared, both RX and TX have the same frame sync length. If the FSL0 bit is set, RX and TX have different frame sync lengths. FSL0 is ignored when the SYN bit is set. 7.5.4.3.3 Word-Length Frame Sync and Data-Word Timing The FSR bit controls the relative timing of the word-length frame sync relative to the data word timing. When the FSR bit is cleared, the word length frame sync is generated (or expected) with the first bit of the data word. Freescale Semiconductor, Inc... MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 7-41 Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) Operating Modes When the FSR bit is set, the word length frame sync is generated (or expected) with the last bit of the previous word. FSR is ignored when a bit length frame sync is selected. 7.5.4.3.4 Frame Sync Polarity The FSP bit controls the polarity of the frame sync. When the FSP bit is cleared, the polarity of the frame sync is positive (i.e., the frame sync signal is asserted high). The ESSI synchronizes on the leading edge of the frame sync signal. Freescale Semiconductor, Inc... When the FSP bit is set, the polarity of the frame sync is negative (i.e., the frame sync is asserted low). The ESSI synchronizes on the trailing edge of the frame sync signal. The ESSI receiver looks for a receive frame sync edge (leading edge if FSP is cleared, trailing edge if FSP is set) only when the previous frame is completed. If the frame sync is asserted before the frame is completed (or before the last bit of the frame is received in the case of a bit frame sync or a word length frame sync with FSR set), the current frame sync is not recognized, and the receiver is internally disabled until the next frame sync. Frames do not have to be adjacent, that is, a new frame sync does not have to follow immediately the previous frame. Gaps of arbitrary periods can occur between frames. All the enabled transmitters are tri-stated during these gaps. 7.5.4.4 Byte Format (LSB/MSB) for the Transmitter Some devices, such as codecs, require a MSB-first data format. Other devices, such as those that use the AES-EBU digital audio format, require the LSB first. To be compatible with all formats, the shift registers in the ESSI are bidirectional. The MSB/LSB selection is made by programming the SHFD bit in the CRB. If the SHFD bit is cleared, data is shifted into the receive shift register MSB first and shifted out of the transmit shift register MSB first. If the SHFD bit is set, data is shifted into the receive shift register LSB first and shifted out of the transmit shift register LSB first. 7.5.5 Flags Two ESSI signals (SC[1:0]) are available for use as serial I/O flags. Their operation is controlled by the SYN, SCD[1:0], SSC1, and TE[2:1] bits in the CRB/CRA.The control bits OF[1:0] and status bits IF[1:0] are double-buffered to/from SC[1:0]. Double-buffering the flags keeps the flags in sync with TX and RX. 7-42 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) GPIO Signals and Registers The SC[1:0] flags are available in synchronous mode only. Each flag can be separately programmed. Flag SC0 is enabled when transmitter 1 is disabled (TE1 = 0). The flagOs direction is selected by the SCD0 bit. When SCD0 is set, SC0 is configured as output. When SCD0 is cleared, SC0 is configured as input. Similarly, the SC1 flag is enabled when transmitter 2 is disabled (TE2 = 0) and the SC1 signal is not configured as transmitter drive enable (Bit SSC1 = 0). SC1Os direction is selected by the SCD1 bit. When SCD1 is set, SC1 is an output flag. When SCD1 is cleared, SC1 is an input flag. Freescale Semiconductor, Inc... When programmed as input flags, the value of the SC[1:0] bits are latched at the same time as the first bit of the receive data word is sampled. Once the input has been latched, the signal on the input flag signal (SC0 and SC1) can change without affecting the input flag. The value of SC[1:0] does not change until the first bit of the next data word is received. When the received data word is latched by RX, the latched values of SC[1:0] are latched by the respective SSISR IF[1:0] bits and can be read by software. When programed as output flags, the value of the SC[1:0] bits is taken from the value of the OF[1:0] bits. The value of the OF[1:0] bits is latched when the contents of TX are transferred to the transmit shift register. The value on SC[1:0] is stable from the time the first bit of the transmit data word is transmitted until the first bit of the next transmit data word is transmitted. The OF[1:0] values can be set directly by software. This allows the DSP56309 to control data transmission by indirectly controlling the value of the SC[1:0] flags. 7.6 GPIO SIGNALS AND REGISTERS The GPIO functionality of an ESSI port (C, D) is controlled by three registers: port control register (PCRC, PCRD), port direction register (PRRC, PRRD) and port data register (PDRC, PDRD). 7.6.1 Port Control Register (PCR) The read/write, 24-bit PCR controls the functionality of the ESSI GPIO signals. Each of PC[5:0] bits controls the functionality of the corresponding port signal. When a PC[i] bit is set, the corresponding port signal is configured as a ESSI signal. When a PC[i] bit is cleared, the corresponding port signal is configured as a GPIO signal. Either a hardware MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 7-43 Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) GPIO Signals and Registers RESET signal or a software RESET instruction clears all PCR bits. Figure 7-18 shows the PCR bits. 7 6 5 PC5 STDn 15 14 13 4 PC4 SRDn 12 3 PC3 2 PC2 1 PC1 0 PC0 0 = GPIO, 1 = ESSI PCRC: ESSI0, PCRD: ESSI1 SCKn SCKn2 SCKn1 SCKn0 11 10 9 8 23 22 21 20 19 18 17 16 Freescale Semiconductor, Inc... Reserved Bit, Read As Zero, Should Be Written With Zero For Future Compatibility AA0688 Figure 7-18 Port Control Register (PCR) (PCRC X:$FFFFBF) (PCRD X:$FFFFAF) 7.6.2 Port Direction Register (PRR) The read/write, 24-bit PRR controls the data direction of the ESSI GPIO signals. When PRR[i] is set, the corresponding signal is an output signal. When PRR[i] is cleared, the corresponding signal is an input signal. Figure 7-19 shows the PRR bits. 7 6 5 PDC5 STDn 15 14 13 4 PDC4 SRDn 12 3 PDC3 2 PDC2 1 PDC1 0 PDC0 0 = Input, 1 = Output PRRC: ESSI0, PRRD: ESSI1 SCKn SCKn2 SCKn1 SCKn0 11 10 9 8 23 22 21 20 19 18 17 16 Reserved Bit, Read As Zero, Should Be Written With Zero For Future Compatibility AA0689 Figure 7-19 Port Direction Register (PRR)(PRRC X:$FFFFBE) (PRRD X:$FFFFAE) 7-44 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) GPIO Signals and Registers Note: Either a hardware RESET signal or a software RESET instruction clears all PRR bits. Table 7-5 shows the port signal configurations. Table 7-5 Port Control Register and Port Direction Register Bits PC[i] 1 PDC[i] X 0 1 Port Signal[i] Function ESSI GPIO input GPIO output Freescale Semiconductor, Inc... 0 0 Note: X: The signal setting is irrelevant to port signal [i] function. 7.6.3 Port Data Register (PDR) The read/write, 24-bit PDR is used to read or write data to and from the ESSI GPIO signals. The PD[5:0] bits are used to read or write data from and to the corresponding port signals if they are configured as GPIO signals. If a port signal [i] is configured as a GPIO input, then the corresponding PD[i] bit reflects the value present on this signal. If a port signal [i] is configured as a GPIO output, then the value written into the corresponding PD[i] bit is reflected on the this signal. Figure 7-20 shows the PDR bits. 7 6 5 PD5 STDn 4 PD4 SRDn 3 PD3 2 PD2 1 PD1 0 PD0 PDRD: ESSI0, PDRD: ESSI1 SCKn SCKn2 SCKn1 SCKn0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 Reserved Bit, Read As Zero, Should Be Written With Zero For Future Compatibility AA0690 Figure 7-20 Port Data Register (PDR) (PDRC X:$FFFFBD) (PDRD X:$FFFFAD) MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 7-45 Freescale Semiconductor, Inc. Enhanced Synchronous Serial Interface (ESSI) GPIO Signals and Registers Note: Either a hardware RESET signal or a software RESET instruction clears all PDR bits. Freescale Semiconductor, Inc... 7-46 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. SECTION 8 Freescale Semiconductor, Inc... SERIAL COMMUNICATION INTERFACE (SCI) MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 8-1 Freescale Semiconductor, Inc. Serial Communication Interface (SCI) 8.1 8.2 8.3 8.4 8.5 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 SCI I/O SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 SCI PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . . 8-4 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21 GPIO SIGNALS AND REGISTERS. . . . . . . . . . . . . . . . . . . 8-27 Freescale Semiconductor, Inc... 8-2 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Serial Communication Interface (SCI) Introduction 8.1 INTRODUCTION The DSP56309 serial communication interface (SCI) provides a full-duplex port for serial communication to other DSPs, microprocessors, or peripherals such as modems. The SCI interfaces without additional logic to peripherals that use TTL-level signals. With a small amount of additional logic, the SCI can connect to peripheral interfaces that have non-TTL level signals, such as the RS232C, RS422, etc. This interface uses three dedicated signals: transmit data (TXD), receive data (RXD), and SCI serial clock (SCLK). It supports industry-standard asynchronous bit rates and protocols, as well as high-speed synchronous data transmission. The asynchronous protocols supported by the SCI include a multidrop mode for master/slave operation with wakeup on idle line and wakeup on address bit capability. This mode allows the DSP56309 to share a single serial line efficiently with other peripherals. The SCI consists of separate transmit and receive sections that can operate asynchronously with respect to each other. A programmable baud-rate generator provides the transmit and receive clocks. An enable vector and an interrupt vector have been included so that the baud-rate generator can function as a general purpose timer when it is not being used by the SCI, or when the interrupt timing is the same as that used by the SCI. Freescale Semiconductor, Inc... 8.2 SCI I/O SIGNALS Each of the three SCI signals (RXD, TXD, and SCLK) can be configured as either a GPIO signal or as a specific SCI signal. Each signal is independent of the others. For example, if only the TXD signal is needed, the RXD and SCLK signals can be programmed for GPIO. However, at least one of the three signals must be selected as an SCI signal to release the SCI from reset. SCI interrupts can be enabled by programming the SCI control registers before any of the SCI signals are programmed as SCI functions. In this case, only one transmit interrupt can be generated because the transmit data register is empty. The timer and timer interrupt operate regardless of how the SCI pins are configuredNeither as SCI or GPIO. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 8-3 Freescale Semiconductor, Inc. Serial Communication Interface (SCI) SCI Programming Model 8.2.1 Receive Data (RXD) This input signal receives byte-oriented serial data and transfers the data to the SCI receive shift register. Asynchronous input data is sampled on the positive edge of the receive clock (1 SCLK) if SCKP is cleared. RXD can be configured as a GPIO signal (PE0) when the SCI RXD function is not being used. 8.2.2 Transmit Data (TXD) Freescale Semiconductor, Inc... This output signal transmits serial data from the SCI transmit shift register. Data changes on the negative edge of the asynchronous transmit clock (SCLK) if SCKP is cleared. This output is stable on the positive edge of the transmit clock. TXD can be programmed as a GPIO signal (PE1) when the SCI TXD function is not being used. 8.2.3 SCI Serial Clock (SCLK) This bidirectional signal provides an input or output clock from which the transmit and/or receive baud rate is derived in asynchronous mode and from which data is transferred in synchronous mode. SCLK can be programmed as a GPIO signal (PE2) when the SCI SCLK function is not being used. This signal can be programmed as PE2 when data is being transmitted on TXD, since the clock does not need to be transmitted in asynchronous mode. Because SCLK is independent of SCI data I/O, there is no connection between programming the PE2 signal as SCLK and data coming out the TXD signal. 8.3 SCI PROGRAMMING MODEL The SCI programming model can be viewed as three types of registers: Control SCI control register (SCR) in Figure 8-1 SCI clock control register (SCCR) in Figure 8-3 SCI status register (SSR) in Figure 8-2 Status Data transfer 8-4 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Serial Communication Interface (SCI) SCI Programming Model SCI Receive Data Registers (SRX) in Figure 8-7 on page 8-19 SCI Transmit Data Registers (STX) in Figure 8-7 SCI Transmit Data Address Register (STXA) in Figure 8-7 The SCI also supports the GPIO functions documented in Section 8NGPIO Signals and Registers on page 8-27. The following paragraphs describe each bit in the programming model. Beginning on page 8-6, Figure 8-4 shows the formats of data words. 7 WOMS 6 RWU 14 STIR 22 5 WAKE 13 TMIE 21 4 SBK 12 TIE 20 3 SSFTD 11 RIE 19 2 WDS2 10 ILIE 18 1 WDS1 9 TE 17 0 WDS0 8 RE 16 REIE AA0854 Freescale Semiconductor, Inc... 15 SCKP 23 Figure 8-1 SCI Control Register (SCR) 7 R8 15 6 FE 14 5 PE 13 4 OR 12 3 IDLE 11 2 RDRF 10 1 TDRE 9 0 TRNE 8 23 22 21 20 19 18 17 16 AA0855 Figure 8-2 SCI Status Register (SSR) 7 CD7 15 TCM 23 6 CD6 14 RCM 22 5 CD5 13 SCP 21 4 CD4 12 COD 20 3 CD3 11 CD11 19 2 CD2 10 CD10 18 1 CD1 9 CD9 17 0 CD0 8 CD8 16 Reserved bit - read as 0 should be written with 0 for future compatibility AA0856 Figure 8-3 SCI Clock Control Register (SCCR) MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 8-5 Freescale Semiconductor, Inc. Serial Communication Interface (SCI) SCI Programming Model SSFTD = 0 Mode 0 0 WDS2 0 WDS1 0 WDS0 D0 D1 D2 D3 D4 D5 D6 D7 8-bit Synchronous Data (Shift Register Mode) TX (SSFTD = 0) One Byte From Shift Register Mode 2 0 1 WDS1 0 WDS0 D0 D1 D2 D3 D4 D5 D6 D7 or Data Type Stop Bit 10-bit Asynchronous (1 Start, 8 Data, 1 Stop) Freescale Semiconductor, Inc... WDS2 TX (SSFTD = 0) Start Bit Mode 4 1 WDS2 0 WDS1 0 WDS0 D0 D1 D2 D3 D4 D5 D6 D7 or Data Type Even Parity Stop Bit 11-bit Asynchronous (1 Start, 8 Data, 1 Even Parity, 1 Stop) TX (SSFTD = 0) Start Bit Mode 5 1 WDS2 0 WDS1 1 WDS0 D7 or Data Type Odd Parity Stop Bit 11-bit Asynchronous (1 Start, 8 Data, 1 Odd Parity, 1 Stop) TX (SSFTD = 0) Start Bit D0 D1 D2 D3 D4 D5 D6 Mode 6 1 WDS2 1 WDS1 0 WDS0 D0 D1 D2 D3 D4 D5 D6 D7 Data Type Stop Bit 11-bit Asynchronous Multidrop (1 Start, 8 Data, 1 Data Type, 1 Stop) TX (SSFTD = 0) Start Bit Data Type: 1 = Address Byte 0 = Data Byte Note: 1. Modes 1, 3, and 7 are reserved. 2. D0 = LSB; D7 = MSB 3. Data is transmitted and received LSB first if SSFTD = 0, or MSB first if SSFTD = 1 AA0691 Figure 8-4 SCI Data Word Formats 8-6 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Serial Communication Interface (SCI) SCI Programming Model SSFTD = 1 Mode 0 0 WDS2 0 WDS1 0 WDS0 D7 D6 D5 D4 D3 D2 D1 D0 8-bit Synchronous Data (Shift Register Mode) TX (SSFTD = 1) One Byte From Shift Register Mode 2 Freescale Semiconductor, Inc... 0 WDS2 1 WDS1 0 WDS0 10-bit Asynchronous (1 Start, 8 Data, 1 Stop) TX (SSFTD = 1) Start Bit D7 D6 D5 D4 D3 D2 D1 D0 or Data Type Stop Bit Mode 4 1 WDS2 0 WDS1 0 WDS0 D0 or Data Type Even Parity Stop Bit 11-bit Asynchronous (1 Start, 8 Data, 1 Even Parity, 1 Stop) TX (SSFTD = 1) Start Bit D7 D6 D5 D4 D3 D2 D1 Mode 5 1 WDS2 0 WDS1 1 WDS0 D0 or Data Type Odd Parity Stop Bit 11-bit Asynchronous (1 Start, 8 Data, 1 Odd Parity, 1 Stop) TX (SSFTD = 1) Start Bit D7 D6 D5 D4 D3 D2 D1 Mode 6 1 WDS2 1 WDS1 0 WDS0 Data Type Stop Bit 11-bit Asynchronous Multidrop (1 Start, 8 Data, 1 Data Type, 1 Stop) TX (SSFTD = 1) Start Bit D7 D6 D5 D4 D3 D2 D1 D0 Data Type: 1 = Address Byte 0 = Data Byte Note: 1. Modes 1, 3, and 7 are reserved. 2. D0 = LSB; D7 = MSB 3. Data is transmitted and received LSB first if SSFTD = 0, or MSB first if SSFTD = 1 AA0691 (cont.) Figure 8-4 SCI Data Word Formats (Continued) MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 8-7 Freescale Semiconductor, Inc. Serial Communication Interface (SCI) SCI Programming Model 8.3.1 SCI Control Register (SCR) The SCR is a 24-bit, read/write register that controls the serial interface operation. Seventeen of the twenty-four bits are currently defined. Each bit is described in the following paragraphs. 8.3.1.1 SCR Word Select (WDS[0:2]) Bits 02 The word select WDS[0:2] bits select the format of transmitted and received data. Format modes are listed in Table 8-1 below and shown in Figure 8-4 on page 8-6. Freescale Semiconductor, Inc... Table 8-1 Word Formats WDS2 0 0 0 0 1 1 1 1 WDS1 0 0 1 1 0 0 1 1 WDS0 0 1 0 1 0 1 0 1 Mode 0 1 2 3 4 5 6 7 Word Formats 8-bit synchronous data (shift register mode) Reserved 10-bit asynchronous (1 start, 8 data, 1 stop) Reserved 11-bit asynchronous (1 start, 8 data, 1 even parity, 1 stop) 11-bit asynchronous (1 start, 8 data, 1 odd parity, 1 stop) 11-bit multidrop asynchronous (1 start, 8 data, 1 data type, 1 stop) Reserved Asynchronous modes are compatible with most UART-type serial devices and support standard RS232C communication links. Multidrop asynchronous mode is compatible with the MC68681 DUART, the M68HC11 SCI interface, and the Intel 8051 serial interface. Synchronous data mode is essentially a high-speed shift register used for I/O expansion and stream-mode channel interfaces. A gated transmit and receive clock compatible with the Intel 8051 serial interface mode 0 makes it possible for you to synchronize data. When odd parity is selected, the transmitter counts the number of 1s in the data word. If the total is not an odd number, the parity bit is set, thus producing an odd number. If the receiver counts an even number of 1s, an error in transmission has occurred. When even parity is selected, an even number must result from the calculation performed at both ends of the line, or an error in transmission has occurred. 8-8 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Serial Communication Interface (SCI) SCI Programming Model The word select bits are cleared by either a hardware RESET signal or a software RESET instruction. 8.3.1.2 SCR SCI Shift Direction (SSFTD) Bit 3 The SSFTD bit determines the order in which the SCI data shift registers shift data in or out: MSB first when set, LSB first when cleared. The parity and data type bits do not change their position in the frame; they remain adjacent to the stop bit. SSFTD is cleared by either a hardware RESET signal or a software RESET instruction. 8.3.1.3 SCR Send Break (SBK) Bit 4 A break is an all-zero word frameNa start bit 0, characters of all 0s (including any parity), and a stop bit 0 (i.e., ten or eleven 0s, depending on the mode selected). If SBK is set and then cleared, the transmitter completes transmission of the current frame, sends ten or eleven 0s (depending on WDS mode), and reverts to idle or sending data. If SBK remains set, the transmitter continually sends whole frames of 0s (ten or eleven bits with no stop bit). At the completion of the break code, the transmitter sends at least one high (set) bit before transmitting any data to guarantee recognition of a valid start bit. Break can be used to signal an unusual condition, message, etc. by forcing a frame error, which is caused by a missing stop bit. Either a hardware RESET signal or a software RESET instruction clears SBK. 8.3.1.4 SCR Wakeup Mode Select (WAKE) Bit 5 When WAKE is cleared, the wakeup on idle line mode is selected. In the wakeup on idle line mode, the SCI receiver is reenabled by an idle string of at least ten or eleven (depending on WDS mode) consecutive 1s. The transmitterOs software must provide this idle string between consecutive messages. The idle string cannot occur within a valid message because each word frame contains a start bit that is 0. When WAKE is set, the wakeup on address bit mode is selected. In the wakeup on address bit mode, the SCI receiver is reenabled when the last (eighth or ninth) data bit received in a character (frame) is 1. The ninth data bit is the address bit (R8) in the 11-bit multidrop mode; the eighth data bit is the address bit in the 10-bit asynchronous and 11-bit asynchronous with parity modes. Thus, the received character is an address that has to be processed by all sleeping processorsNthat is, each processor has to compare the received character with its own address and decide whether to receive or ignore all following characters. Either a hardware RESET signal or a software RESET instruction clears WAKE. Freescale Semiconductor, Inc... 8.3.1.5 SCR Receiver Wakeup Enable (RWU) Bit 6 When RWU is set and the SCI is in an asynchronous mode, the wakeup function is enabledNthat is, the SCI is asleep, and can be awakened by the event defined by the WAKE bit. In the sleep state, all interrupts and all receive flags except IDLE are disabled. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 8-9 Freescale Semiconductor, Inc. Serial Communication Interface (SCI) SCI Programming Model When the receiver wakes up, RWU is cleared by the wakeup hardware. The programmer can also clear the RWU bit to wake up the receiver. RWU can be used by the programmer to ignore messages that are for other devices on a multidrop serial network. Wakeup on idle line (WAKE is cleared) or wakeup on address bit (WAKE is set) must be chosen. 1. When WAKE is cleared and RWU is set, the receiver does not respond to data on the data line until an idle line is detected. Freescale Semiconductor, Inc... 2. When WAKE is set and RWU is set, the receiver does not respond to data on the data line until a data frame with the address bit set is detected. When the receiver wakes up, the RWU bit is cleared, and the first frame of data is received. If interrupts are enabled, the CPU is interrupted and the interrupt routine reads the message header to determine if the message is intended for this DSP. 1. If the message is for this DSP, the message is received, and RWU is set to wait for the next message. 2. If the message is not for this DSP, the DSP immediately sets RWU. Setting RWU causes the DSP to ignore the remainder of the message and wait for the next message. Either a hardware RESET signal or a software RESET instruction clears RWU. RWU is ignored in synchronous mode. 8.3.1.6 SCR Wired-OR Mode Select (WOMS) Bit 7 When the WOMS bit is set, the SCI TXD driver is programmed to function as an open-drain output and can be wired together with other TXD signals in an appropriate bus configuration, such as a master-slave multidrop configuration. An external pullup resistor is required on the bus. When the WOMS is cleared, the TXD signal uses an active internal pullup. Either a hardware RESET signal or a software RESET instruction clears WOMS. 8.3.1.7 SCR Receiver Enable (RE) Bit 8 When RE is set, the receiver is enabled. When RE is cleared, the receiver is disabled, and data transfer from the receive shift register to the receive data register (SRX) is inhibited. If RE is cleared while a character is being received, the reception of the character is completed before the receiver is disabled. RE does not inhibit RDRF or receive interrupts. Either a hardware RESET signal or a software RESET instruction clears RE. 8.3.1.8 SCR Transmitter Enable (TE) Bit 9 When TE is set, the transmitter is enabled. When TE is cleared, the transmitter completes transmission of data in the SCI Transmit Data Shift Register, then the serial output is 8-10 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Serial Communication Interface (SCI) SCI Programming Model forced high (i.e., idle). Data present in the SCI transmit data register (STX) is not transmitted. STX can be written and TDRE cleared, but the data is not transferred into the shift register. TE does not inhibit TDRE or transmit interrupts. Either a hardware RESET signal or a software RESET instruction clears TE. Setting TE causes the transmitter to send a preamble of ten or eleven consecutive 1s (depending on WDS). This procedure gives the programmer a convenient way to insure that the line goes idle before starting a new message. To force this separation of messages by the minimum idle line time, the following sequence is recommended: 1. Write the last byte of the first message to STX. Freescale Semiconductor, Inc... 2. Wait for TDRE to go high, indicating the last byte has been transferred to the transmit shift register. 3. Clear TE and set TE. This queues an idle line preamble to follow immediately the transmission of the last character of the message (including the stop bit). 4. Write the first byte of the second message to STX. In this sequence, if the first byte of the second message is not transferred to STX prior to the finish of the preamble transmission, the transmit data line marks idle until STX is finally written. 8.3.1.9 SCR Idle Line Interrupt Enable (ILIE) Bit 10 When ILIE is set, the SCI interrupt occurs when IDLE (SCI status register bit 3) is set. When ILIE is cleared, the IDLE interrupt is disabled. Either a hardware RESET signal or a software RESET instruction clears ILIE. An internal flag, the shift register idle interrupt (SRIINT) flag, is the interrupt request to the interrupt controller. SRIINT is not directly accessible to the user. When a valid start bit has been received, an idle interrupt is generated if both IDLE and ILIE are set. The idle interrupt acknowledge from the interrupt controller clears this interrupt request. The idle interrupt is not asserted again until at least one character has been received. The results are as follows: 1. The IDLE bit shows the real status of the receive line at all times. 2. An idle interrupt is generated once for each idle state, no matter how long the idle state lasts. 8.3.1.10 SCR SCI Receive Interrupt Enable (RIE) Bit 11 The RIE bit is set to enable the SCI Receive Data interrupt. If RIE is cleared, the Receive Data interrupt is disabled, and then the RDRF bit in the SCI Status Register must be MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 8-11 Freescale Semiconductor, Inc. Serial Communication Interface (SCI) SCI Programming Model polled to determine if the receive data register is full. If both RIE and RDRF are set, the SCI requests an SCI receive data interrupt from the interrupt controller. Receive interrupts with exception have higher priority than normal receive data interrupts. Therefore, if an exception occurs (i.e., if PE, FE, or OR are set) and REIE is set, the SCI requests an SCI receive data with exception interrupt from the interrupt controller. Either a hardware RESET signal or a software RESET instruction clears RIE. 8.3.1.11 SCR SCI Transmit Interrupt Enable (TIE) Bit 12 The TIE bit is set to enable the SCI transmit data interrupt. If TIE is cleared, transmit data interrupts are disabled, and the transmit data register empty (TDRE) bit in the SCI status register must be polled to determine if the transmit data register is empty. If both TIE and TDRE are set, the SCI requests an SCI transmit data interrupt from the interrupt controller. Either a hardware RESET signal or a software RESET instruction clears TIE. 8.3.1.12 SCR Timer Interrupt Enable (TMIE) Bit 13 The TMIE bit is set to enable the SCI timer interrupt. If TMIE is set, timer interrupt requests are sent to the interrupt controller at the rate set by the SCI clock register. The timer interrupt is automatically cleared by the timer interrupt acknowledge from the interrupt controller. This feature allows DSP programmers to use the SCI baud rate generator as a simple periodic interrupt generator if the SCI is not in use, if external clocks are used for the SCI, or if periodic interrupts are needed at the SCI baud rate. The SCI internal clock is divided by 16 (to match the 1 SCI baud rate) for timer interrupt generation. This timer does not require that any SCI signals be configured for SCI use to operate. Either a hardware RESET signal or a software RESET instruction clears TMIE. 8.3.1.13 SCR Timer Interrupt Rate (STIR) Bit 14 The STIR bit controls a divide-by-32 in the SCI Timer interrupt generator. When STIR is cleared, the divide-by-32 is inserted in the chain. When STIR is set, the divide-by-32 is bypassed, thereby increasing timer resolution by a factor of 32. Either a hardware RESET signal or a software RESET instruction clears this bit. To insure proper operation of the timer, STIR must not be changed during timer operation (i.e., if TMIE = 1). 8.3.1.14 SCR SCI Clock Polarity (SCKP) Bit 15 The SCKP bit controls the clock polarity sourced or received on the clock signal (SCLK), eliminating the need for an external inverter. When SCKP is cleared, the clock polarity is positive. When SCKP is set, the clock polarity is negative. In synchronous mode, positive polarity means that the clock is normally positive and transitions negative during valid data. Negative polarity means that the clock is normally negative and transitions positive during valid data. In asynchronous mode, positive polarity means that the rising edge of the clock occurs in the center of the period that data is valid. Negative polarity means that the falling edge of the clock occurs during the center of the period Freescale Semiconductor, Inc... 8-12 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Serial Communication Interface (SCI) SCI Programming Model that data is valid. Either a hardware RESET signal or a software RESET instruction clears SCKP. 8.3.1.15 Receive with Exception Interrupt Enable (REIE) Bit 16 The REIE bit is set to enable the SCI receive data with exception interrupt. If REIE is cleared, the receive data with exception interrupt is disabled. If both REIE and RDRF are set, and PE, FE, and OR are not all cleared, the SCI requests an SCI receive data with exception interrupt from the interrupt controller. Either a hardware RESET signal or a software RESET instruction clears REIE. Freescale Semiconductor, Inc... 8.3.2 SCI Status Register (SSR) The SSR is a 24-bit, read-only register used by the DSP to determine the status of the SCI. The status bits are described in the following paragraphs. 8.3.2.1 SSR Transmitter Empty (TRNE) Bit 0 The TRNE flag bit is set when both the transmit shift register and transmit data register (STX) are empty to indicate that there is no data in the transmitter. When TRNE is set, data written to one of the three STX locations or to the transmit data address register (STXA) is transferred to the transmit shift register and is the first data transmitted. TRNE is cleared when TDRE is cleared by writing data into the STX or the STXA, or when an idle, preamble, or break is transmitted. This bit, when set, indicates that the transmitter is empty; therefore, the data written to STX or STXA is transmitted next. That is, there is no word in the transmit shift register presently being transmitted. This procedure is useful when initiating the transfer of a message (i.e., a string of characters). TRNE is set by a hardware RESET signal, software RESET instruction, SCI individual reset, or STOP instruction. 8.3.2.2 SSR Transmit Data Register Empty (TDRE) Bit 1 The TDRE flag bit is set when the SCI transmit data register is empty. When TDRE is set, new data can be written to one of the SCI transmit data registers (STX) or the transmit data address register (STXA). TDRE is cleared when the SCI transmit data register is written. TDRE is set by the hardware RESET signal, software RESET instruction, SCI individual reset, or STOP instruction. In synchronous mode, when using the internal SCI clock, there is a delay of up to 5.5 serial clock cycles between the time that STX is written until TDRE is set, indicating the data has been transferred from the STX to the transmit shift register. There is a 2 to 4 serial clock cycle delay between writing STX and loading the transmit shift register; in addition, TDRE is set in the middle of transmitting the second bit. When using an external serial transmit clock, if the clock stops, the SCI transmitter stops. TDRE is not set MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 8-13 Freescale Semiconductor, Inc. Serial Communication Interface (SCI) SCI Programming Model until the middle of the second bit transmitted after the external clock starts. Gating the external clock off after the first bit has been transmitted delays TDRE indefinitely. In asynchronous mode, the TDRE flag is not set immediately after a word is transferred from the STX or STXA to the transmit shift register nor when the word first begins to be shifted out. TDRE is set two cycles of the 16 clock after the start bitN that is, two 16 clock cycles into the transmission time of the first data bit. 8.3.2.3 SSR Receive Data Register Full (RDRF) Bit 2 The RDRF bit is set when a valid character is transferred to the SCI Receive Data Register from the SCI receive shift register (regardless of the error bits condition). RDRF is cleared when the SCI receive data register is read or by a hardware RESET signal, software RESET instruction, SCI individual reset, or STOP instruction. 8.3.2.4 SSR Idle Line Flag (IDLE) Bit 3 IDLE is set when 10 (or 11) consecutive 1s are received. IDLE is cleared by a start-bit detection. The IDLE status bit represents the status of the receive line. The transition of IDLE from 0 to 1 can cause an IDLE interrupt (ILIE). IDLE is cleared by a hardware RESET signal, software RESET instruction, SCI individual reset, or STOP instruction. 8.3.2.5 SSR Overrun Error Flag (OR) Bit 4 The OR flag bit is set when a byte is ready to be transferred from the receive shift register to the receive data register (SRX) that is already full (RDRF = 1). The receive shift register data is not transferred to the SRX. The OR flag indicates that character(s) in the received data stream may have been lost. The only valid data is located in the SRX. OR is cleared when the SCI Status Register is read, followed by a read of SRX. The OR bit clears the FE and PE bitsNthat is, an overrun error has higher priority than FE or PE. OR is cleared by a hardware RESET signal, software RESET instruction, SCI individual reset, or STOP instruction. 8.3.2.6 SSR Parity Error (PE) Bit 5 In the 11-bit asynchronous modes, the PE bit is set when an incorrect parity bit has been detected in the received character. It is set simultaneously with RDRF for the byte which contains the parity errorNthat is, when the received word is transferred to the SRX. If PE is set, further data transfer into the SRX is not inhibited. PE is cleared when the SCI status register is read, followed by a read of SRX. PE is also cleared by a hardware RESET signal, software RESET instruction, SCI individual reset, or STOP instruction. In 10-bit asynchronous mode, 11-bit multidrop mode, and 8-bit synchronous mode, the PE bit is always cleared since there is no parity bit in these modes. If the byte received causes both parity and overrun errors, the SCI receiver recognizes only the overrun error. Freescale Semiconductor, Inc... 8-14 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Serial Communication Interface (SCI) SCI Programming Model 8.3.2.7 SSR Framing Error Flag (FE) Bit 6 The FE bit is set in asynchronous modes when no stop bit is detected in the data string received. FE and RDRE are set simultaneously when the received word is transferred to the SRX. However, the FE flag inhibits further transfer of data into the SRX until it is cleared. FE is cleared when the SCI status register is read followed by reading the SRX. A hardware RESET signal, software RESET instruction, SCI individual reset, or STOP instruction also clears FE. In 8-bit synchronous mode, FE is always cleared. If the byte received causes both framing and overrun errors, the SCI receiver recognizes only the overrun error. Freescale Semiconductor, Inc... 8.3.2.8 SSR Received Bit 8 (R8) Address Bit 7 In 11-bit asynchronous multidrop mode, the R8 bit is used to indicate whether the received byte is an address or data. R8 is set for addresses and is cleared for data. R8 is not affected by reading the SRX or SCI status register. A hardware RESET signal, software RESET instruction, SCI individual reset, or STOP instruction also clears R8. 8.3.3 SCI Clock Control Register (SCCR) The SCCR is a 24-bit, read/write register that controls the selection of the clock modes and baud rates for the transmit and receive sections of the SCI interface. The control bits are described in the following paragraphs. The SCCR is cleared by a hardware RESET signal. The basic features of the clock generator (as in Figure 8-5 on page 8-16 and Figure 8-6 on page 8-18) are these: The SCI logic always uses a 16 internal clock in asynchronous modes and always uses a 2 internal clock in synchronous mode. The maximum internal clock available to the SCI peripheral block is the oscillator frequency divided by 4. The 16 clock is necessary for asynchronous modes to synchronize the SCI to the incoming data, as in Figure 8-5. For asynchronous modes, the user must provide a 16 clock to use an external baud rate generator (i.e., SCLK input). For asynchronous modes, the user can select either 1 or 16 for the output clock when using internal TX and RX clocks (TCM = 0 and RCM = 0). When SCKP is cleared, the transmitted data on the TXD signal changes on the negative edge of the 1 serial clock and is stable on the positive edge. When SCKP is set, the data changes on the positive edge and is stable on the negative edge. The received data on the RXD signal is sampled on the positive edge (if SCKP = 0) or on the negative edge (if SCKP = 1) of the 1 serial clock. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 8-15 Freescale Semiconductor, Inc. Serial Communication Interface (SCI) SCI Programming Model For asynchronous mode, the output clock is continuous. For synchronous mode, a 1 clock is used for the output or input baud rate. The maximum 1 clock is the crystal frequency divided by 8. For synchronous mode, the clock is gated. For synchronous mode, the transmitter and receiver are synchronous with each other. Select 8-or 9-bit Words Idle Line 0 1 2 3 4 5 6 7 8 Freescale Semiconductor, Inc... RX, TX Data (SSFTD = 0) Start Stop Start x1 Clock x16 Clock (SCKP = 0) AA0692 Figure 8-5 16 x Serial Clock 8.3.3.1 SCCR Clock Divider (CD[11:0]) Bits 110 The CD[11:0] bits specify the divide ratio of the prescale divider in the SCI clock generator. A divide ratio from 1 to 4096 (CD[11:0] = $000 to $FFF) can be selected. Either a hardware RESET signal or a software RESET instruction clears CD11CD0. 8.3.3.2 SCCR Clock Out Divider (COD) Bit 12 The clock output divider is controlled by COD and SCI mode. If SCI mode is synchronous, the output divider is fixed at divide by 2. If SCI mode is asynchronous, then one of the following conditions occurs: If COD is cleared and SCLK is an output (i.e., TCM and RCM are both cleared), the SCI clock is divided by 16 before being output to the SCLK signal. Thus, the SCLK output is a 1 clock. If COD is set and SCLK is an output, the SCI clock is fed directly out to the SCLK signal. Thus, the SCLK output is a 16 baud clock. Either a hardware RESET signal or a software RESET instruction clears COD. 8-16 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Serial Communication Interface (SCI) SCI Programming Model 8.3.3.3 SCCR SCI Clock Prescaler (SCP) Bit 13 The SCP bit selects a divide by 1 (SCP is cleared) or divide by 8 (SCP is set) prescaler for the clock divider. The output of the prescaler is further divided by 2 to form the SCI clock. Either a hardware RESET signal or a software RESET instruction clears SCP. 8.3.3.4 SCCR Receive Clock Mode Source (RCM) Bit 14 RCM selects whether an internal or external clock is used for the receiver. If RCM is cleared, the internal clock is used. If RCM is set, the external clock (from the SCLK signal) is used. Either a hardware RESET signal or a software RESET instruction clears RCM. Freescale Semiconductor, Inc... Table 8-2 TCM and RCM Bit Configuration TCM 0 0 1 1 RCM 0 1 0 1 TX Clock Internal Internal External External RX Clock Internal External Internal External SCLK Signal Output Input Input Input Mode Synchronous/Asynchronous Asynchronous Only Asynchronous Only Synchronous/Asynchronous MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 8-17 Freescale Semiconductor, Inc. Serial Communication Interface (SCI) SCI Programming Model Fcore Divide By 2 12-bit Counter Prescaler: Divide by 1 or 8 Divide By 2 CD11CD0 SCP Internal Clock Freescale Semiconductor, Inc... Divide By 16 Timer Interrupt (STMINT) SCI Core Logic Uses Divide by 16 for Asynchronous Uses Divide by 2 for Synchronous If Asynchronous Divide by 1 or 16 If Synchronous Divide By 2 COD BPS = F core 64 ((7 SCP + 1) CD + 1) SCP = 0 or 1 CD = $000 to $FFF SCKP SCKP = 0 SCKP = 1 + where: TO SCLK AA0693 Figure 8-6 SCI Baud Rate Generator 8.3.3.5 SCCR Transmit Clock Source Bit (TCM) Bit 15 TCM selects whether an internal or external clock is used for the transmitter. If TCM is cleared, the internal clock is used. If TCM is set, the external clock (from the SCLK signal) is used. Either a hardware RESET signal or a software RESET instruction clears TCM. 8.3.4 SCI Data Registers The SCI data registers are divided into two groups: receive and transmit (as in Figure 8-7). There are two receive registersNa receive data register (SRX) and a serial-to-parallel receive shift register. There are also two transmit registersNa transmit data register (called either STX or STXA) and a parallel-to-serial transmit shift register. 8-18 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Serial Communication Interface (SCI) SCI Programming Model 23 SRX 16 15 87 0 SCI Receive Data Register High (Read Only) SRX SRX SCI Receive Data Register Middle (Read Only) SCI Receive Data Register Low (Read Only) RXD SCI Receive Data Shift Register Note: 1. SRX is the same register decoded at three different addresses. (a) Receive Data Register Freescale Semiconductor, Inc... 23 STX 16 15 87 0 SCI Transmit Data Register High (Write Only) STX STX SCI Transmit Data Register Middle (Write Only) SCI Transmit Data Register Low (Write Only) SCI Transmit Data Shift Register TXD 23 16 15 87 STXA 0 SCI Transmit Data Address Register (Write Only) Note: 1. Bytes are masked on the fly. 2. STX is the same register decoded at four different addresses. (b) Transmit Data Register AA0694 Figure 8-7 SCI Programming Model Data Registers 8.3.4.1 SCI Receive Registers (SRX) Data bits received on the RXD signal are shifted into the SCI receive shift register. When a complete word has been received, the data portion of the word is transferred to the byte-wide SRX. This process converts the serial data to parallel data and provides double-buffering. Double-buffering provides flexibility to the programmer and increased throughput since the programmer can save (and process) the previous word while the current word is being received. The SRX can be read at three locations as SRXL, SRXM, and SRXH. When SRXL is read, the contents of the SRX are placed in the lower byte of the data bus and the remaining bits on the data bus are read as 0s. Similarly, when SRXM is read, the contents of SRX are placed in the middle byte of the bus, and when SRXH is read, the contents of SRX are placed in the high byte with the remaining bits read as 0s. Mapping SRX as described allows three bytes to be efficiently packed into one 24-bit word by ORing three data bytes read from the three addresses. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 8-19 Freescale Semiconductor, Inc. Serial Communication Interface (SCI) SCI Programming Model The length and format of the serial word are defined by the WDS0, WDS1, and WDS2 control bits in the SCR. The clock source is defined by the receive clock mode (RCM) select bit in the SCR. In synchronous mode, the start bit, the eight data bits, the address/data indicator bit and/or the parity bit, and the stop bit are received in that order. Data bits are sent LSB first if SSFTD is cleared, and MSB first if SSFTD is set. In synchronous mode, the synchronization is provided by gating the clock. In either synchronous or asynchronous mode, when a complete word has been clocked in, the contents of the shift register can be transferred to the SRX and the flags; RDRF, FE, PE, and OR are changed appropriately. Because the operation of the receive shift register is transparent to the DSP, the contents of this register are not directly accessible to the programmer. 8.3.4.2 SCI Transmit Registers The transmit data register is a one byte-wide register mapped into four addresses as STXL, STXM, STXH, and STXA. In asynchronous mode, when data is to be transmitted, STXL, STXM, and STXH are used. When STXL is written, the low byte on the data bus is transferred to the STX. When STXM is written, the middle byte is transferred to the STX. When STXH is written, the high byte is transferred to the STX. This structure makes it easy for the programmer to unpack the bytes in a 24-bit word for transmission. TDXA should be written in the 11-bit asynchronous multidrop mode when the data is an address and it is desired that the ninth bit (the address bit) be set. When STXA is written, the data from the low byte on the data bus is stored in it. The address data bit is cleared in the 11-bit asynchronous multidrop mode when any of STXL, STXM or STXH is written. When either STX (STXL, STXM, or STXH) or STXA is written, TDRE is cleared. The transfer from either STX or STXA to the transmit shift register occurs automatically, but not immediately, when the last bit from the previous word has been shifted out; that is, the transmit shift register is empty. Like the receiver, the transmitter is double-buffered. However, a 2 to 4 serial clock cycle delay occurs between when the data is transferred from either STX or STXA to the transmit shift register and when the first bit appears on the TXD signal. (A serial clock cycle is the time required to transmit one data bit). The transmit shift register is not directly addressable, and a dedicated flag for this register does not exist. Because of this fact and the 2 to 4 cycle delay, two bytes cannot be written consecutively to STX or STXA without polling, as the second byte might overwrite the first byte. The TDRE flag should always be polled prior to writing STX or STXA to prevent overruns unless transmit interrupts have been enabled. Either STX or STXA is usually written as part of the interrupt service routine. An interrupt is generated only if TDRE is set. The transmit shift register is indirectly visible via the TRNE bit in the SSR. Freescale Semiconductor, Inc... 8-20 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Serial Communication Interface (SCI) Operating Modes In synchronous mode, data is synchronized with the transmit clock, which can have either an internal or external source, as defined by the TCM bit in the SCCR. The length and format of the serial word is defined by the WDS0, WDS1, and WDS2 control bits in the SCR. In asynchronous modes, the start bit, the eight data bits (with the LSB first if SSFTD = 0 and the MSB first if SSFTD = 1), the address/data indicator bit or parity bit, and the stop bit are transmitted in that order. The data to be transmitted can be written to any one of the three STX addresses. If SCKP is set and SSHTD is set, the SCI synchronous mode is equivalent to the SSI operation in the 8-bit data on-demand mode. Freescale Semiconductor, Inc... Note: When writing data to a peripheral device, there is a two cycle pipeline delay until any status bits affected by this operation are updated. If you read any of those status bits within the next two cycles, the bit does not reflect its current status. See the DSP56300 Family Manual, Appendix B, Polling a Peripheral Device for Write for further details. 8.4 OPERATING MODES The operating modes for the DSP56309 SCI are these: 8-bit synchronous (shift register mode) 10-bit asynchronous (1 start, 8 data, 1 stop) 11-bit asynchronous (1 start, 8 data, 1 even parity, 1 stop) 11-bit asynchronous (1 start, 8 data, 1 odd parity, 1 stop) 11-bit multidrop asynchronous (1 start, 8 data, 1 data type, 1 stop) This mode is used for master/slave operation with wakeup on idle line and wakeup on address bit capability. It allows the DSP56309 to share a single serial line efficiently with other peripherals. These modes are selected using the WD[0:2] bits in the SCR. The synchronous data mode is essentially a high-speed shift register used for I/O expansion and stream-mode channel interfaces. Data synchronization is accomplished by the use of a gated transmit and receive clock that is compatible with the IntelO 8051 serial interface mode 0. Asynchronous modes are compatible with most UART-type serial devices. Standard RS232C communication links are supported by these modes. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 8-21 Freescale Semiconductor, Inc. Serial Communication Interface (SCI) Operating Modes The multidrop asynchronous modes are compatible with the MC68681 DUART, the M68HC11 SCI interface, and the Intel 8051 serial interface. 8.4.1 SCI After Reset There are four different methods of resetting the SCI. 1. Hardware RESET signal Freescale Semiconductor, Inc... 2. Software RESET instruction: Both hardware and software resets clear the port control register bits, which configure all I/O as GPIO input. The SCI remains in the reset state as long as all SCI signals are programmed as GPIO (PC2, PC1, and PC0 all are cleared); the SCI becomes active only when at least one of the SCI I/O signals is not programmed as GPIO. 3. Individual reset: During program execution, the PC2, PC1, and PC0 bits can be cleared (individual reset), which causes the SCI to stop serial activity and enter the reset state. All SCI status bits are set to their reset state. However, the contents of the SCR are not affected, allowing the DSP program to reset the SCI separately from the other internal peripherals. During individual reset, internal DMA accesses to the data registers of the SCI are not valid and the data read is unknown. 4. Stop processing state reset: Executing the STOP instruction halts operation of the SCI until the DSP is restarted, causing the SSR to be reset. No other SCI registers are affected by the STOP instruction. Table 8-3 on page 8-23 illustrates how each type of reset affects each register in the SCI. 8-22 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Serial Communication Interface (SCI) Operating Modes Table 8-3 SCI Registers after Reset Reset Type Register Bit Bit Mnemonic Bit Number HW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 SW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 IR Reset N N N N N N N N N N N N N N N 0 0 0 0 0 0 1 ST Reset N N N N N N N N N N N N N N N 0 0 0 0 0 0 1 REIE SCKP STIR 16 15 14 13 12 11 10 9 8 7 6 5 4 3 20 7 6 5 4 3 2 1 Freescale Semiconductor, Inc... TMIE TIE RIE ILIE TE SCR RE WOMS RWU WAKE SBK SSFTD WDS[2:0] R8 FE PE SSR OR IDLE RDRF TDRE MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 8-23 Freescale Semiconductor, Inc. Serial Communication Interface (SCI) Operating Modes Table 8-3 SCI Registers after Reset (Continued) Reset Type Register Bit Bit Mnemonic Bit Number HW Reset 1 0 0 0 0 0 N N N N SW Reset 1 0 0 0 0 0 N N N N IR Reset 1 N N N N N N N N N ST Reset 1 N N N N N N N N TRNE TCM RCM 0 15 14 13 12 110 2316, 158, 70 230 80 80 Freescale Semiconductor, Inc... SCCR SCP COD CD[11:0] SRX STX SRSH STSH Note: SRX [23:0] STX[23:0] SRS[8:0] STS[8:0] SRSHNSCI Receive Shift Register, STSH N SCI Transmit Shift Register HWNHardware reset is caused by asserting the external RESET signal. SWNSoftware reset is caused by executing the RESET instruction. IRNIndividual reset is caused by clearing PCRE (bits 02) (configured for GPIO). STNStop reset is caused by executing the STOP instruction. 1NThe bit is set during this reset. 0NThe bit is cleared during this reset. N N The bit is not changed during this reset 8.4.2 SCI Initialization The correct way to initialize the SCI is as follows: 1. Send a hardware RESET signal or software RESET instruction. 2. Program SCI control registers. 3. Configure at least one SCI signal as other than GPIO. 8-24 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Serial Communication Interface (SCI) Operating Modes If interrupts are to be used, the signals must be selected, and interrupts must be enabled and unmasked before the SCI can operate. The order does not matter; any one of these three requirements for interrupts can be used to enable the SCI. Synchronous applications usually require exact frequencies, which require that the crystal frequency be chosen carefully. An alternative to selecting the system clock to accommodate the SCI requirements is to provide an external clock to the SCI. 8.4.3 SCI Initialization Example Freescale Semiconductor, Inc... One way to initialize the SCI is described here as an example. 1. The SCI should be in its individual reset state (PCR = $0). 2. Configure the control registers (SCR, SCCR) according to the operating mode, but do not enable either transmitter (TE = 0) or receiver (RE = 0). It is possible to set the interrupt enable bits that would be in use during the operation (no interrupt occurs). 3. Enable the SCI by setting the PCR bits according to which signals will be in use during operation. 4. If transmit interrupt is not used, write data to the transmitter. If transmitter interrupt enable is set, an interrupt is issued and the interrupt handler should write data into the transmitter. SCI transmit request is serviced by DMA channel if it is programmed to service the SCI transmitter. 5. Enable transmitters (TE = 1) and receiver (RE = 1), according to usage. Operation starts as follows: For an internally generated clock, the SCLK signal starts operation immediately after the SCI is enabled (Step 3 above) for asynchronous modes. In synchronous mode, the SCLK signal is active only while transmitting (gated clock). Data is received only when the receiver is enabled (RE = 1) and after the occurrence of the SCI receive sequence on the RXD signal, as defined by the operating mode (i.e., idle line sequence). Data is transmitted only after the transmitter is enabled (TE = 1), and after transmitting the initialization sequence depending on the operating mode. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 8-25 Freescale Semiconductor, Inc. Serial Communication Interface (SCI) Operating Modes 8.4.4 Preamble, Break, and Data Transmission Priority Two or three transmission commands can be set simultaneously: 1. A preamble (TE is set.) 2. A break (SBK is set or is cleared.) 3. There is data for transmission (TDRE is cleared.) After the current character transmission, if two or more of these commands are set, the transmitter executes them in the following order: Freescale Semiconductor, Inc... 1. Preamble 2. Break 3. Data 8.4.5 SCI Exceptions The SCI can cause five different exceptions in the DSP. These exceptions are as follows (ordered from the highest to the lowest priority): 1. SCI receive data with exception status is caused by receive data register full with a receiver error (parity, framing, or overrun error). Clearing the pending interrupt is done by reading the SCI status register, followed by a read of SRX. A long interrupt service routine should be used to handle the error condition. This interrupt is enabled by SCR bit 16 (REIE). 2. SCI receive data is caused by receive data register full. Reading SRX clears the pending interrupt. This error-free interrupt can use a fast interrupt service routine for minimum overhead. This interrupt is enabled by SCR bit 11 (RIE). 3. SCI transmit data is caused by transmit data register empty. Writing STX clears the pending interrupt. This error-free interrupt can use a fast interrupt service routine for minimum overhead. This interrupt is enabled by SCR bit 12 (TIE). 4. SCI idle line is caused by the receive line entering the idle state (10 or 11 bits of 1s). This interrupt is latched and then automatically reset when the interrupt is accepted. This interrupt is enabled by SCR bit 10 (ILIE). 5. SCI timer is caused by the baud rate counter reaching zero. This interrupt is automatically reset when the interrupt is accepted. This interrupt is enabled by SCR bit 13 (TMIE). 8-26 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Serial Communication Interface (SCI) GPIO Signals and Registers 8.5 GPIO SIGNALS AND REGISTERS The GPIO functionality of port SCI is controlled by three registers: Port E control register (PCRE), Port E direction register (PRRE) and Port E data register (PDRE). 8.5.1 Port E Control Register (PCRE) Freescale Semiconductor, Inc... The read/write, 24-bit PCRE controls the functionality of SCI GPIO signals. Each of the PC[2:0] bits controls the functionality of the corresponding port signal. When a PC[i] bit is set, the corresponding port signal is configured as a SCI signal. When a PC[i] bit is cleared, the corresponding port signal is configured as a GPIO signal. Bits in the Port E control register appear in Figure 8-8. 7 6 5 4 3 2 PC2 1 PC1 0 PC0 Port Control Bits: 1 = SCI 0 = GPIO 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 Reserved Bit, Read as 0, Should be Written with 0 for Future Compatibility AA0695 Figure 8-8 Port E Control Register (PCRE) Note: A hardware RESET signal or a software RESET instruction clears all PCR bits. 8.5.2 Port E Direction Register (PRRE) The read/write, 24-bit PRRE controls the direction of SCI GPIO signals. When port signal[i] is configured as GPIO, PDC[i] controls the port signal direction. When PDC[i] is set, the GPIO port signal[i] is configured as output. When PDC[i] is cleared, the GPIO port signal[i] is configured as input. Bits in the Port E direction register appear in Figure 8-9. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 8-27 Freescale Semiconductor, Inc. Serial Communication Interface (SCI) GPIO Signals and Registers 7 6 5 4 3 2 1 0 PDC2 PDC1 PDC0 Direction Control Bits: 1 = Output 0 = Input 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 Reserved Bit, Read as 0, Should be Written with 0 for Future Compatibility Freescale Semiconductor, Inc... AA0696 Figure 8-9 Port E Direction Register (PRRE) Note: A hardware RESET signal or a software RESET instruction clears all PRR bits. Table 8-4 shows the port signal configurations. Table 8-4 Port Control Register and Port Direction Register Bits PC[i] 1 0 0 PDC[i] 1 or 0 0 1 Port Signal[i] Function SCI GPIO input GPIO output 8.5.3 Port E Data Register (PDRE) The read/write, 24-bit PDRE is used to read or write data to or from SCI GPIO signals. Bits PD[2:0] are used to read or write data from or to the corresponding port signals if they are configured as GPIO. If a port signal[i] is configured as a GPIO input, then the corresponding PD[i] bit reflects the value of this signal. If a port signal[i] is configured as a GPIO output, then the value of the corresponding PD[i] bit is reflected on this signal. Bits of the Port E data register appear in Figure 8-10. 8-28 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Serial Communication Interface (SCI) GPIO Signals and Registers 7 6 5 4 3 2 PD2 1 PD1 9 0 PD0 8 15 14 13 12 11 10 23 22 21 20 19 18 17 16 Reserved Bit, Read as 0, Should be Written with 0 for Future Compatibility Freescale Semiconductor, Inc... AA0697 Figure 8-10 Port E Data Register (PDRE) Note: A hardware RESET signal or a software RESET instruction clears all PDRE bits. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 8-29 Freescale Semiconductor, Inc. Serial Communication Interface (SCI) GPIO Signals and Registers Freescale Semiconductor, Inc... 8-30 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. SECTION 9 TRIPLE TIMER MODULE Freescale Semiconductor, Inc... MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 9-1 Freescale Semiconductor, Inc. Triple Timer Module 9.1 9.2 9.3 9.4 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 TRIPLE TIMER MODULE ARCHITECTURE . . . . . . . . . . . . 9-3 TRIPLE TIMER MODULE PROGRAMMING MODEL. . . . . . 9-5 TIMER OPERATIONAL MODES. . . . . . . . . . . . . . . . . . . . . 9-16 Freescale Semiconductor, Inc... 9-2 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Triple Timer Module Introduction 9.1 INTRODUCTION This section describes the internal triple timer module in the DSP56309. Each timer has a single signal that can be used as a GPIO signal or as a timer signal. These three timers can be used to generate timed pulses or as pulse width modulators. They can also be used as an event counter, to capture an event, or to measure the width or period of a signal. 9.2 TRIPLE TIMER MODULE ARCHITECTURE Freescale Semiconductor, Inc... The timer module is composed of a common 21-bit prescaler and three independent and identical general purpose 24-bit timer/event counters, each having its own register set. Each timer can use internal or external clocking and can interrupt the DSP56309 after a specified number of events (clocks) or can signal an external device after counting internal events. Each timer can also be used to trigger DMA transfers after a specified number of events (clocks) has occurred. Each timer connects to the external world through one bidirectional signal, designated TIO0TIO2 for Timers 02, respectively. When the TIO signal is configured as input, the timer functions as an external event counter or measures external pulse width/signal period. When the TIO signal is used as output, the timer functions as a timer, a watchdog timer, or a pulse width modulator. When the TIO signal is not used by the timer, it can be used as a GPIO signal (also called TIO0TIO2). 9.2.1 Triple Timer Module Block Diagram Figure 9-1 shows a block diagram of the triple timer module. This module includes a 24-bit timer prescaler load register (TPLR), a 24-bit timer prescaler count register (TPCR), a 21-bit prescaler clock counter, and three timers. Each of the three timers can use the prescaler clock as its clock source. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 9-3 Freescale Semiconductor, Inc. Triple Timer Module Triple Timer Module Architecture GDB 24 TPLR Timer Prescaler Load Register 24 TPCR 24 24 Timer Prescaler Count Register Timer 0 Freescale Semiconductor, Inc... 21-bit Counter Timer 1 Timer 2 CLK/2 TIO0 TIO1 TIO2 AA0673 Figure 9-1 Triple Timer Module Block Diagram 9.2.2 Timer Block Diagram The timer block diagram (in Figure 9-2) shows the structure of a timer module. The timer programmerOs model (in Figure 9-3 on page 9-6) shows the structure of the timer registers. The three timers are identical in structure and function. A generic timer is discussed in this section. The timer includes a 24-bit counter, a 24-bit read/write timer control and status register (TCSR), a 24-bit read-only timer count register (TCR), a 24-bit write-only timer load register (TLR), a 24-bit read/write timer compare register (TCPR), and logic for clock selection and interrupt/DMA trigger generation. The timer mode is controlled by the TC[3:0] bits of the timer control/status register (TCSR). For a listing of the timer modes, see Section 9NTimer Operational Modes. For a description of their operation, see Section 9.4.1NTiming Modes. 9-4 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Triple Timer Module Triple Timer Module Programming Model The DSP56309 views each timer as a memory-mapped peripheral with four registers occupying four 24-bit words in the X data memory space. Either standard polled or interrupt programming techniques can be used to service the timers. The timer programming model is shown in Figure 9-3 on page 9-6. GDB 24 24 24 TLR Load Register 24 TCR Count Register 24 TCPR Compare Register Freescale Semiconductor, Inc... TCSR Control/Status Register 9 2 24 24 24 24 Timer Control Logic Counter = Timer interrupt/ DMA request TIO CLK/2 prescaler CLK AA0676 Figure 9-2 Timer Module Block Diagram 9.3 TRIPLE TIMER MODULE PROGRAMMING MODEL The programming model for the triple timer module appears in Figure 9-3 on page 9-6. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 9-5 Freescale Semiconductor, Inc. Triple Timer Module Triple Timer Module Programming Model 23 0 Timer Prescaler Load Register (TPLR) TPLR = $FFFF83 23 0 Timer Prescaler Count Register (TPCR) TPLR = $FFFF82 Freescale Semiconductor, Inc... 7 TC3 15 PCE 23 6 5 4 3 2 1 0 TE 8 Timer Control/Status Register (TCSR) TCSR0 = $FFFF8F TCSR1 = $FFFF8B TCSR2 = $FFFF87 TC2 TC1 TC0 14 13 DO 22 21 12 DI 20 11 DIR 19 TCIE TOIE 10 9 TRM INV 18 17 16 TCF TOF 23 0 Timer Load Register (TLR) TLR0 = $FFFF8E TLR1 = $FFFF8A TLR2 = $FFFF86 23 0 Timer Compare Register (TCPR) TCPR0 = $FFFF8D TCPR1 = $FFFF89 TCPR2 = $FFFF85 23 0 Timer Count Register (TCR) TCR0 = $FFFF8C TCR1 = $FFFF88 TCR2 = $FFFF84 - reserved, read as 0, should be written with 0 for future compatibility Figure 9-3 Timer Module ProgrammerOs Model 9-6 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Triple Timer Module Triple Timer Module Programming Model 9.3.1 Prescaler Counter The prescaler counter is a 21-bit counter that is decremented on the rising edge of the prescaler input clock. The counter is enabled when at least one of the three timers is enabled (i.e., one or more of the timer enable (TE) bits are set) and is using the prescaler output as its source (i.e., one or more of the PCE bits are set). 9.3.2 Timer Prescaler Load Register (TPLR) Freescale Semiconductor, Inc... The TPLR is a 24-bit, read/write register that controls the prescaler divide factor (i. e., the number that the prescaler counter loads and begins counting from) and the source for the prescaler input clock. The control bits are shown below in Figure 9-4. 23 22 PS1 11 PL11 10 PL10 21 PS0 9 PL9 20 PL20 8 PL8 19 PL19 7 PL7 18 PL18 6 PL6 17 PL17 5 PL5 16 PL16 4 PL4 15 PL15 3 PL3 14 PL14 2 PL2 13 PL13 1 PL1 12 PL12 0 PL0 N reserved, read as 0, should be written with 0 for future compatibility Figure 9-4 Timer Prescaler Load Register (TPLR) 9.3.2.1 TPLR Prescaler Preload Value (PL[20:0]) Bits 20-0 These 21 bits contain the prescaler preload value. This value is loaded into the prescaler counter when the counter value reaches 0, or the counter switches state from disabled to enabled. If PL[20:0] = N, then the prescaler counts N + 1 source clock cycles before generating a prescaler clock pulse. Therefore, the prescaler divide factor = (preload value) + 1. The PL[20:0] bits are cleared by a hardware RESET signal or a software RESET instruction. 9.3.2.2 TPLR Prescaler Source (PS[1:0]) Bits 22-21 The two PS bits control the source of the prescaler clock. Table 9-1 summarizes PS bit functionality. The prescalerOs use of a TIO signal is not affected by the TCSR settings of the timer corresponding to the TIO signal being used. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 9-7 Freescale Semiconductor, Inc. Triple Timer Module Triple Timer Module Programming Model If the prescaler source clock is external, the prescaler counter is incremented by signal transitions on the TIO signal. The external clock is internally synchronized to the internal clock. The external clock frequency must be lower than the DSP56309 internal operating frequency divided by 4 (CLK/4). The PS[1:0] bits are cleared by a hardware RESET signal or a software RESET instruction. Note: To insure proper operation, change the PS[1:0] bits only when the prescaler counter is disabled. Disable the prescaler counter by clearing the TE bit in the TCSR of each of three timers. Table 9-1 Prescaler Source Selection PS1 0 0 1 1 PS0 0 1 0 1 Prescaler Clock Source Internal CLK/2 TIO0 TIO1 TIO2 Freescale Semiconductor, Inc... 9.3.2.3 TPLR Reserved Bit 23 This reserved bit is read as 0 and should be written with 0 for future compatibility. 9.3.3 Timer Prescaler Count Register (TPCR) The TPCR is a 24-bit, read-only register that reflects the current value in the prescaler counter. The register bits are shown in Figure 9-5. 23 22 21 20 PC20 11 PC11 10 PC10 9 PC9 8 PC8 19 PC19 7 PC7 18 PC18 6 PC6 17 PC17 5 PC5 16 PC16 4 PC4 15 PC15 3 PC3 14 PC14 2 PC2 13 PC13 1 PC1 12 PC12 0 PC0 N reserved, read as 0, should be written with 0 for future compatibility Figure 9-5 Timer Prescaler Count Register (TPCR) 9-8 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Triple Timer Module Triple Timer Module Programming Model 9.3.3.1 TPCR Prescaler Counter Value (PC[20:0]) Bits 20-0 These 21 bits contain the current value of the prescaler counter. 9.3.3.2 TPCR Reserved Bits 23-21 These reserved bits are read as 0 and should be written with 0 for future compatibility. 9.3.4 Timer Control/Status Register (TCSR) Freescale Semiconductor, Inc... The TCSR is a 24-bit, read/write register controlling the timer and reflecting its status. The register bits are shown in Figure 9-6. The control and status bits are documented in Table 9-2 on page 9-10. 23 22 21 TCF 11 DIR 10 9 TRM 20 TOF 8 INV 7 TC3 6 TC2 5 TC1 4 TC0 19 18 17 16 15 PCE 3 2 TCIE 14 13 DO 1 TOIE 12 DI 0 TE N reserved, read as 0, should be written with 0 for future compatibility Figure 9-6 Timer Control/Status Register 9.3.4.1 Timer Enable (TE) Bit 0 The TE bit is used to enable or disable the timer. Setting TE enables the timer and clears the timer counter. The counter starts counting according to the mode selected by the timer control (TC[3:0]) bit values. Clearing the TE bit disables the timer. The TE bit is cleared by a hardware RESET signal or a software RESET instruction. Note: When all three timers are disabled and the signals are not in GPIO mode, all three TIO signals are tri-stated. To prevent undesired spikes on the TIO signals when switching from tri-state into active state, these signals should be tied to the high or low signal state by the use of pull-up or pull-down resistors. 9.3.4.2 Timer Overflow Interrupt Enable (TOIE) Bit 1 The TOIE bit is used to enable the timer overflow interrupts. Setting TOIE enables overflow interrupt generation. The timer counter can hold a maximum value of $FFFFFF. When the counter value is at the maximum value and a new event causes the counter to be incremented to $000000, the timer generates an overflow interrupt. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 9-9 Freescale Semiconductor, Inc. Triple Timer Module Triple Timer Module Programming Model Clearing the TOIE bit disables overflow interrupt generation. The TOIE bit is cleared by a hardware RESET signal or a software RESET instruction. 9.3.4.3 Timer Compare Interrupt Enable (TCIE) Bit 2 The TCIE bit is used to enable or disable the timer compare interrupts. Setting TCIE enables the compare interrupts. In the timer, pulse width modulation (PWM), or watchdog modes, a compare interrupt is generated after the counter value matches the value of the TCPR. The counter starts counting up from the number loaded from the TLR and if the TCPR value is N, an interrupt occurs after (N M + 1) events, where M is the value of TLR. Freescale Semiconductor, Inc... Clearing the TCIE bit disables the compare interrupts. The TCIE bit is cleared by a hardware RESET signal or a software RESET instruction. 9.3.4.4 Timer Control (TC[3:0]) Bits 4-7 The four TC bits control the source of the timer clock, the behavior of the TIO signal, and timer mode. Table 9-2 summarizes the TC bit functionality. There is a detailed description of the timer operating modes in Section 9.4NTimer Operational Modes. The TC bits are cleared by a hardware RESET signal or a software RESET instruction. Note: If the clock is external, the counter is incremented by the transitions on the TIO signal. The external clock is internally synchronized to the internal clock, and its frequency should be lower than the internal operating frequency divided by 4 (CLK/4). To insure proper operation, the TC[3:0] bits should be changed only when the timer is disabled (i.e., when the TE bit in the TCSR has been cleared). Table 9-2 Timer Control Bits Bit Settings TC3 0 0 0 0 TC2 0 0 0 0 TC1 0 0 1 1 TC0 0 1 0 1 Mode Number 0 1 2 3 Mode Characteristics Mode Function Timer and GPIO Timer Pulse Timer Toggle Event Counter TIO GPIO 1 Output Output Input Clock Internal Internal Internal External Note: 9-10 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Triple Timer Module Triple Timer Module Programming Model Table 9-2 Timer Control Bits (Continued) Bit Settings TC3 0 0 TC2 1 1 1 1 0 0 0 0 1 1 1 1 TC1 0 0 1 1 0 0 1 1 0 0 1 1 TC0 0 1 0 1 0 1 0 1 0 1 0 1 Mode Number 4 5 6 7 8 9 10 11 12 13 14 15 Mode Characteristics Mode Function Input Width Measurement Input Period Measurement Capture Event Pulse Width Modulation (PWM) Reserved Watchdog Pulse Watchdog Toggle Reserved Reserved Reserved Reserved Reserved TIO Input Input Input Output N Output Output N N N N N Clock Internal Internal Internal Internal N Internal Internal N N N N N Freescale Semiconductor, Inc... 0 0 1 1 1 1 1 1 1 1 Note 1: The GPIO function is enabled only if all of the TC[3:0] bits are 0. 9.3.4.5 Inverter (INV) Bit 8 The Inverter (INV) bit affects the polarity definition of the incoming signal on the TIO signal when TIO is programmed as input. It also affects the polarity of the output pulse generated on the TIO signal when TIO is programmed as output. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 9-11 Freescale Semiconductor, Inc. Triple Timer Module Triple Timer Module Programming Model The inverter bit operation is described below in Table 9-3. Table 9-3 Inverter (INV) Bit Operation TIO Programmed as Input Mode INV = 0 0 GPIO signal on the TIO signal read directly Counter is incremented on the rising edge of the signal from the TIO signal Counter is incremented on the rising edge of the signal from the TIO signal Counter is incremented on the rising edge of the signal from the TIO signal Width of the high input pulse is measured Period is measured between the rising edges of the input signal Event is captured on the rising edge of the signal from the TIO signal INV = 1 GPIO signal on the TIO signal inverted Counter is incremented on the falling edge of the signal from the TIO signal Counter is incremented on the falling edge of the signal from the TIO signal Counter is incremented on the falling edge of the signal from the TIO signal Width of the low input pulse is measured Period is measured between the falling edges of the input signal Event is captured on the falling edge of the signal from the TIO signal INV = 0 Bit written to GPIO put on TIO signal directly N INV = 1 Bit written to GPIO inverted and put on TIO signal N TIO Programmed as Output Freescale Semiconductor, Inc... 1 2 TCRx output put on TIO signal directly TCRx output inverted and put on TIO signal 3 N N 4 N N 5 N N 6 N N 9-12 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Triple Timer Module Triple Timer Module Programming Model Table 9-3 Inverter (INV) Bit Operation (Continued) TIO Programmed as Input Mode INV = 0 7 N INV = 1 N INV = 0 Pulse generated by the timer has positive polarity Pulse generated by the timer has positive polarity Pulse generated by the timer has positive polarity. INV = 1 Pulse generated by the timer has negative polarity Pulse generated by the timer has negative polarity Pulse generated by the timer has negative polarity TIO Programmed as Output 9 N N Freescale Semiconductor, Inc... 10 N N The INV bit is cleared by a hardware RESET signal or a software RESET instruction. The INV bit affects both the timer and GPIO modes. To insure correct operation, this bit should be changed only when one or both of the following conditions is true: The timer has been disabled by clearing the TE bit in the TCSR. The timer is in GPIO mode. The INV bit does not affect the polarity of the prescaler source when the TIO is used as input to the prescaler. 9.3.4.6 Timer Reload Mode (TRM) Bit 9 The TRM bit controls the counter preload operation. In timer (03) and watchdog (910) modes, the counter is preloaded with the TLR value after the TE bit is set and the first internal or external clock signal is received. If the TRM bit is set, the counter is reloaded each time after it reaches the value contained by the TCR. In PWM mode (7), the counter is reloaded each time counter overflow occurs. In measurement (45) modes, if the TRM and the TE bits are set, the counter is preloaded with the TLR value on each appropriate edge of the input signal. If the TRM bit is cleared, the counter operates as a free running counter and is incremented on each incoming event. The TRM bit is cleared by a hardware RESET signal or a software RESET instruction. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 9-13 Freescale Semiconductor, Inc. Triple Timer Module Triple Timer Module Programming Model 9.3.4.7 Direction (DIR) Bit 11 The DIR bit determines the behavior of the TIO signal when it is used as a GPIO signal. When the DIR bit is set, the TIO signal is an output; when the DIR bit is cleared, the TIO signal is an input. The TIO signal can be used as a GPIO signal only when all of the TC[3:0] bits are cleared. If any of the TC[3:0] bits are set, then the GPIO function is disabled and the DIR bit has no effect. The DIR bit is cleared by a hardware RESET signal or a software RESET instruction. 9.3.4.8 Data Input (DI) Bit 12 The DI bit reflects the value of the TIO signal. If the INV bit is set, the value of the TIO signal is inverted before it is written to the DI bit. If the INV bit is cleared, the value of the TIO signal is written directly to the DI bit. DI is cleared by a hardware RESET signal or a software RESET instruction. 9.3.4.9 Data Output (DO) Bit 13 The DO bit is the source of the TIO value when it is a data output signal. The TIO signal is data output when GPIO mode is enabled and DIR is set. A value written to the DO bit is written to the TIO signal. If the INV bit is set, the value of the DO bit is inverted when written to the TIO signal. When the INV bit is cleared, the value of the DO bit is written directly to the TIO signal. When GPIO mode is disabled, writing the DO bit has no effect. The DO bit is cleared by a hardware RESET signal or a software RESET instruction. 9.3.4.10 Prescaler Clock Enable (PCE) Bit 15 The PCE bit is used to select the prescaler clock as the timer source clock. When the PCE bit is cleared, the timer uses either an internal (CLK/2) signal or an external (TIO) signal as its source clock. When the PCE bit is set, the prescaler output is used as the timer source clock for the counter regardless of the timer operating mode. To insure proper operation, the PCE bit should be changed only when the timer is disabled (when the TE bit is cleared). Which source clock is used for the prescaler is determined by the PS[1:0] bits of the TPLR. A timer can be clocked by a prescaler clock that is derived from the TIO of another timer. 9.3.4.11 Timer Overflow Flag (TOF) Bit 20 The TOF bit is set to indicate that counter overflow has occurred. This bit is cleared by writing a 1 to the TOF bit. Writing a 0 to the TOF bit has no effect. The bit is also cleared when the timer overflow interrupt is serviced. The TOF bit is cleared by a hardware RESET signal, a software RESET instruction, the STOP instruction, or by clearing the TE bit to disable the timer. Freescale Semiconductor, Inc... 9-14 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Triple Timer Module Triple Timer Module Programming Model 9.3.4.12 Timer Compare Flag (TCF) Bit 21 The TCF bit is set to indicate that the event count is complete. In the timer, PWM, and watchdog modes, the TCF bit is set when (N M + 1) events have been counted. (N is the value in the compare register and M is the TLR value.) In measurement modes, the TCF bit is set when the measurement is completed. Writing a 1 into the TCF bit clears this bit. Writing a 0 into the TCF bit has no effect. The bit is also cleared when the timer compare interrupt is serviced. The TCF bit is cleared by a hardware RESET signal, a software RESET instruction, the STOP instruction, or by clearing the TE bit to disable the timer. Freescale Semiconductor, Inc... Note: The TOF and TCF bits are cleared by writing a 1 to the specific bit. In order to insure that only the desired bit is cleared, do not use the BSET command. The proper way to clear these bits is to write (using a MOVEP instruction) a 1 to the flag to be cleared and a 0 to the other flag. 9.3.4.13 TCSR Reserved Bits 3, 10, 14, 16-19, 22, 23 These reserved bits are read as 0 and should be written with 0 for future compatibility. 9.3.5 Timer Load Register (TLR) The TLR is a 24-bit, write-only register. In all modes, the counter is preloaded with the TLR value after the TE bit in the TCSR is set and a first event occurs. In timer modes, if the timer reload mode (TRM) bit in the TCSR is set, the counter is reloaded each time after it has reached the value contained by the timer compare register (TCPR) and the new event occurs. In measurement modes, if the TRM bit in the TCSR is set and the TE bit in the TCSR is set, the counter is reloaded with the value in the TLR on each appropriate edge of the input signal. In PWM modes, if the TRM bit in the TCSR is set, the counter is reloaded each time after it has overflowed and the new event occurs. In watchdog modes, if the TRM bit in the TCSR is set, the counter is reloaded each time after it has reached the value contained by the TCPR and the new event occurs. In this mode, the counter is also reloaded whenever the TLR is written with a new value while the TE bit in the TCSR is set. In all modes, if the TRM bit in the TCSR is cleared (TRM = 0), the counter operates as a free-running counter. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 9-15 Freescale Semiconductor, Inc. Triple Timer Module Timer Operational Modes 9.3.6 Timer Compare Register (TCPR) The TCPR is a 24-bit, read/write register that contains the value to be compared to the counter value. These two values are compared every timer clock after the TE bit in the TCSR is set. When the values match, the timer compare flag (TCF) bit is set and an interrupt is generated if interrupts are enabled (if the timer compare interrupt enable (TCIE) bit in the TCSR is set). The TCPR is ignored in measurement modes. 9.3.7 Timer Count Register (TCR) Freescale Semiconductor, Inc... The Timer Count Register (TCR) is a 24-bit, read-only register. In timer and watchdog modes, the counterOs contents can be read at any time by reading the TCR register. In Measurement modes, the TCR is loaded with the current value of the counter on the appropriate edge of the input signal, and its value can be read to determine the width, period, or delay of the leading edge of the input signal. When the timer is in measurement modes, the TIO signal is used for the input signal. 9.4 TIMER OPERATIONAL MODES Each timer has these operational modes to meet a variety of system requirements: Timer GPIO, mode 0: Internal timer interrupt generated by the internal clock Pulse, mode 1: External timer pulse generated by the internal clock Toggle, mode 2: Output timing signal toggled by the internal clock Event counter, mode 3: Internal timer interrupt generated by an external clock Input width, mode 4: Input pulse width measurement Input pulse, mode 5: Input signal period measurement Capture, mode 6: Capture external signal Measurement PWM, mode 7: Pulse width modulation Watchdog Pulse, mode 9: Output pulse, internal clock 9-16 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Triple Timer Module Timer Operational Modes Toggle, mode 10: Output toggle, internal clock These modes are described in detail below. Timer modes are selected by setting the TC[3:0] bits in the TCSR. Table 9-2 on page 9-10 shows how the different timer modes are selected by setting the bits in the TCSR. The table also shows the TIO signal direction and the clock source for each timer mode. That table summarizes these modes, and the following paragraphs describe these modes in detail. Note: To insure proper operation, the TC[3:0] bits should be changed only when the timer is disabled (i.e., when the TE bit in the TCSR is cleared). Freescale Semiconductor, Inc... 9.4.1 Timing Modes The following timing modes are provided: Timer GPIO Timer pulse Timer toggle Event counter 9.4.1.1 Timer GPIO (Mode 0) Bit Settings TC3 0 TC2 0 TC1 0 TC0 0 TIO GPIO Clock Internal Mode Characteristics # 0 Function Timer Name GPIO In this mode, the timer generates an internal interrupt when a counter value is reached (if the timer compare interrupt is enabled). Set the TE bit to clear the counter and enable the timer. Load the value the timer is to count into the TCPR. The counter is loaded with the TLR value when the first timer clock signal is received. The timer clock can be taken from either the DSP56309 clock divided by two (CLK/2) or from the prescaler clock output. Each subsequent clock signal increments the counter. When the counter equals the TCPR value, the TCF bit in TCSR is set, and a compare interrupt is generated if the TCIE bit is set. If the TRM bit in the TCSR is set, the counter MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 9-17 Freescale Semiconductor, Inc. Triple Timer Module Timer Operational Modes is reloaded with the TLR value at the next timer clock and the count is resumed. If the TRM bit is cleared, the counter continues to be incremented on each timer clock signal. This process is repeated until the timer is disabled (i.e., TE is cleared). If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated. The counter contents can be read at any time by reading the TCR. 9.4.1.2 Timer Pulse (Mode 1) Bit Settings TC3 0 TC2 0 TC1 0 TC0 1 TIO Output Clock Internal Mode Characteristics # 1 Function Timer Name Pulse Freescale Semiconductor, Inc... In this mode, the timer generates an external pulse on its TIO signal when the timer count reaches a pre-set value. Set the TE bit to clear the counter and enable the timer. The value to which the timer is to count is loaded into the TCPR. The counter is loaded with the TLR value when the first timer clock signal is received. The TIO signal is loaded with the value of the INV bit. The timer clock signal can be taken from either the DSP56309 clock divided by two (CLK/2) or from the prescaler clock output. Each subsequent clock signal increments the counter. When the counter matches the TCPR value, the TCF bit in TCSR is set and a compare interrupt is generated if the TCIE bit is set. The polarity of the TIO signal is inverted for one timer clock period. If the TRM bit is set, the counter is loaded with the TLR value on the next timer clock and the count is resumed. If the TRM bit is cleared, the counter continues to be incremented on each timer clock. This process is repeated until the TE bit is cleared (disabling the timer). The counter contents can be read at any time by reading TCR. The value of the TLR sets the delay between starting the timer and the generation of the output pulse. To generate successive output pulses with a delay of X clocks between signals, the TLR value should be set to X/2 and the TRM bit should be set. This process is repeated until the timer is disabled (i.e., TE is cleared). 9-18 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Triple Timer Module Timer Operational Modes If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated. The counter contents can be read at any time by reading the TCR. 9.4.1.3 Timer Toggle (Mode 2) Bit Settings TC3 TC2 0 TC1 1 TC0 0 TIO Output Clock Internal Mode Characteristics # 0 Function Timer Name Toggle Freescale Semiconductor, Inc... 0 In this mode, the timer periodically toggles the polarity of the TIO signal. Set the TE bit in the TCR to clear the counter and enable the timer. The value to which the timer is to count is loaded into the TPCR. The counter is loaded with the TLR value when the first timer clock signal is received. The TIO signal is loaded with the value of the INV bit. The timer clock signal can be taken from either the DSP56309 clock divided by two (CLK/2) or from the prescaler clock output. Each subsequent clock signal increments the counter. When the counter value matches the value in the TCPR, the polarity of the TIO output signal is inverted. The TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is set. If the TRM bit is set, the counter is loaded with the value of the TLR when the next timer clock is received, and the count is resumed. If the TRM bit is cleared, the counter continues to be incremented on each timer clock. This process is repeated until the TE bit is cleared, disabling the timer. The counter contents can be read at any time by reading the TCR. The TLR value in the TCPR sets the delay between starting the timer and toggling the TIO signal. To generate output signals with a delay of X clock cycles between toggles, the TLR value should be set to X/2, and the TRM bit should be set. This process is repeated until the timer is disabled (i.e., TE is cleared). If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated. The counter contents can be read at any time by reading the TCR. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 9-19 Freescale Semiconductor, Inc. Triple Timer Module Timer Operational Modes 9.4.1.4 Timer Event Counter (Mode 3) Bit Settings Mode Characteristics TC0 1 TIO Input Clock External # 3 Function Timer Name Event Counter TC3 0 TC2 0 TC1 1 In this mode, the timer counts external events and issues an interrupt when a preset number of events is counted. Freescale Semiconductor, Inc... Set the TE bit to clear the counter and enable the timer. The value to which the timer is to count is loaded into the TPCR. The counter is loaded with the TLR value when the first timer clock signal is received. The timer clock signal can be taken from either the TIO input signal or the prescaler clock output. Each subsequent clock signal increments the counter. If an external clock is used, it must be internally synchronized to the internal clock, and its frequency must be less than the DSP56309 internal operating frequency divided by 4. The value of the INV bit in the TCSR determines whether low-to-high (0 to 1) transitions or high-to-low (1 to 0) transitions increment the counter. If the INV bit is set, high-to-low transitions increment the counter. If the INV bit is cleared, low-to-high transitions increment the counter. When the counter matches the value contained in the TCPR, the TCF bit in the TCSR is set, and a compare interrupt is generated if the TCIE bit is set. If the TRM bit is set, the counter is loaded with the value of the TLR when the next timer clock is received, and the count is resumed. If the TRM bit is cleared, the counter continues to be incremented on each timer clock. This process is repeated until the timer is disabled (i.e., TE is cleared). If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated. The counter contents can be read at any time by reading the TCR. 9.4.2 Signal Measurement Modes The following Signal Measurement modes are provided: Measurement input width 9-20 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Triple Timer Module Timer Operational Modes Measurement input period Measurement capture 9.4.2.1 Measurement Accuracy The external signal is synchronized with the internal clock used to increment the counter. This synchronization process can cause the number of clocks measured for the selected signal value to vary from the actual signal value by plus or minus one counter clock cycle. 9.4.2.2 Measurement Input Width (Mode 4) Bit Settings TC3 0 TC2 1 TC1 0 TC0 0 Mode 4 Mode Characteristics Name Input Width Function Measurement TIO Input Clock Internal Freescale Semiconductor, Inc... In this mode, the timer counts the number of clocks that occur between opposite edges of an input signal. Set the TE bit to clear the counter and enable the timer. Load the timerOs count value into the TLR. After the first appropriate transition (as determined by the INV bit) occurs on the TIO input signal, the counter is loaded with the TLR value on the first timer clock signal received either from the DSP56309 clock divided by two (CLK/2) or from the prescaler clock input. Each subsequent clock signal increments the counter. If the INV bit is set, the timer starts on the first high-to-low (1 to 0) signal transition on the TIO signal. If the INV bit is cleared, the timer starts on the first low-to-high (0 to 1) transition on the TIO signal. When the first transition opposite in polarity to the INV bit setting occurs on the TIO signal, the counter stops. The TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is set. The value of the counter (which measures the width of the TIO pulse) is loaded into the TCR. The TCR can be read to determine the external signal pulse width. If the TRM bit is set, the counter is loaded with the TLR value on the first timer clock received following the next valid transition occurring on the TIO input signal and the count is resumed. If the TRM bit is cleared, the counter continues to be incremented on each timer clock. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 9-21 Freescale Semiconductor, Inc. Triple Timer Module Timer Operational Modes This process is repeated until the timer is disabled (i.e., TE is cleared). If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated. The counter contents can be read at any time by reading the TCR. 9.4.2.3 Measurement Input Period (Mode 5) Bit Settings TC3 TC2 1 TC1 0 TC0 1 Mode 5 Mode Characteristics Name Input Period Function Measurement TIO Input Clock Internal Freescale Semiconductor, Inc... 0 In this mode, the timer counts the period between the reception of signal edges of the same polarity across the TIO signal. Set the TE bit to clear the counter and enable the timer. The value to which the timer is to count is loaded into the TLR. The value of the INV bit determines whether the period is measured between consecutive low-to-high (0 to 1) transitions of TIO or between consecutive high-to-low (1 to 0) transitions of TIO. If INV is set, high-to-low signal transitions are selected. If INV is cleared, low-to-high signal transitions are selected. After the first appropriate transition occurs on the TIO input signal, the counter is loaded with the TLR value on the first timer clock signal received from either the DSP56309 clock divided by two (CLK/2) or the prescaler clock output. Each subsequent clock signal increments the counter. On the next signal transition of the same polarity that occurs on TIO, the TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is set. The contents of the counter are loaded into the TCR. The TCR then contains the value of the time that elapsed between the two signal transitions on the TIO signal. After the second signal transition, if the TRM bit is set, the TE bit is set to clear the counter and enable the timer. The counter is loaded with the TLR value on the first timer clock signal. Each subsequent clock signal increments the counter. After the second signal transition, if the TRM bit is set, the TE bit is set to clear if the TRM bit is cleared, the counter continues to be incremented on each timer clock. This process is repeated until the timer is disabled (i.e., TE is cleared). If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated. The counter contents can be read at any time by reading the TCR. 9-22 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Triple Timer Module Timer Operational Modes 9.4.2.4 Measurement Capture (Mode 6) Bit Settings Mode Characteristics TC0 0 Mode 6 Name Capture Function Measurement TIO Input Clock Internal TC3 0 TC2 1 TC1 1 In this mode, the timer counts the number of clocks that elapse between starting the timer and receiving an external signal. Freescale Semiconductor, Inc... Set the TE bit to clear the counter and enable the timer. The value to which the timer is to count is loaded into the TLR. When the first timer clock signal is received, the counter is loaded with the TLR value. The timer clock signal can be taken from either the DSP56309 clock divided by two (CLK/2) or from the prescaler clock output. Each subsequent clock signal increments the counter. At the first appropriate transition of the external clock detected on the TIO signal, the TCF bit in the TCSR is set and, if the TCIE bit is set, a compare interrupt is generated, the counter halts, and the contents of the counter are loaded into the TCR. The value of the TCR represents the delay between the setting of the TE bit and the detection of the first clock edge signal on the TIO signal. The value of the INV bit determines whether a high-to-low (1 to 0) or low-to-high (0 to 1) transition of the external clock signals the end of the timing period. If the INV bit is set, a high-to-low transition signals the end of the timing period. If INV is cleared, a low-to-high transition signals the end of the timing period. If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated. The counter contents can be read at any time by reading the TCR. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 9-23 Freescale Semiconductor, Inc. Triple Timer Module Timer Operational Modes 9.4.3 Pulse Width Modulation (PWM, Mode 7) Bit Settings TC3 0 TC2 1 TC1 1 TC0 1 Mode 7 Mode Characteristics Name Pulse Width Modulation Function PWM TIO Output Clock Internal Freescale Semiconductor, Inc... In this mode, the timer generates periodic pulses of a preset width. Set the TE bit to clear the counter and enable the timer. The value to which the timer is to count is loaded into the TPCR. When first timer clock is received from either the DSP56309 internal clock divided by two (CLK/2) or the prescaler clock output, the counter is loaded with the TLR value. Each subsequent timer clock increments the counter. When the counter equals the value in the TCPR, the TIO output signal is toggled and the TCF bit in the TCSR is set. The contents of the counter are placed into the TCR. If the TCIE bit is set, a compare interrupt is generated. The counter continues to be incremented on each timer clock. If counter overflow has occurred, the TIO output signal is toggled, the TOF bit in TCSR is set, and an overflow interrupt is generated if the TOIE bit is set. If the TRM bit is set, the counter is loaded with the TLR value on the next timer clock and the count is resumed. If the TRM bit is cleared, the counter continues to be incremented on each timer clock. This process is repeated until the timer is disabled by clearing the TE bit. TIO signal polarity is determined by the value of the INV bit. When the counter is started by setting the TE bit, the TIO signal assumes the value of the INV bit. On each subsequent toggling of the TIO signal, the polarity of the TIO signal is reversed. For example, if the INV bit is set, the TIO signal generates the following signal: 1010. If the INV bit is cleared, the TIO signal generates the following signal: 0101. The counter contents can be read at any time by reading the TCR. The value of the TLR determines the output period ($FFFFFF - TLR + 1). The timer counter increments the initial TLR value and toggles the TIO signal when the counter value exceeds $FFFFFF. 9-24 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Triple Timer Module Timer Operational Modes The duty cycle of the TIO signal is determined by the value in the TCPR. When the value in the TLR is incremented to a value equal to the value in the TCPR, the TIO signal is toggled. The duty cycle is equal to ($FFFFFF TCPR) divided by ($FFFFFF - TLR + 1). For a 50% duty cycle, the value of TCPR is equal to ($FFFFFF + TLR + 1) / 2. Note: The value in TCPR must be greater than the value in TLR. 9.4.4 Watchdog Modes Freescale Semiconductor, Inc... The following watchdog timer modes are provided: Watchdog pulse Watchdog toggle 9.4.4.1 Watchdog Pulse (Mode 9) Bit Settings TC3 1 TC2 0 TC1 0 TC0 1 Mode 9 Name Pulse Mode Characteristics Function Watchdog TIO Output Clock Internal In this mode, the timer generates an external signal at a preset rate. The signal period is equal to the period of one timer clock. Set the TE bit to clear the counter and enable the timer. The value to which the timer is to count is loaded into the TCPR. The counter is loaded with the TLR value on the first timer clock received from either the DSP56309 internal clock divided by two (CLK/2) or the prescaler clock output. Each subsequent timer clock increments the counter. When the counter matches the value of the TCPR, the TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is also set. If the TRM bit is set, the counter is loaded with the TLR value on the next timer clock and the count is resumed. If the TRM bit is cleared, the counter continues to be incremented on each subsequent timer clock. This process is repeated until the timer is disabled (i.e., TE is cleared). MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 9-25 Freescale Semiconductor, Inc. Triple Timer Module Timer Operational Modes If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated. At the same time, a pulse is output on the TIO signal with a pulse width equal to the timer clock period. The pulse polarity is determined by the value of the INV bit. If the INV bit is set, the pulse polarity is high (logical 1). If the INV bit is cleared, the pulse polarity is low (logical 0). The counter contents can be read at any time by reading the TCR. The counter is reloaded whenever the TLR is written with a new value while the TE bit is set. Note: In this mode, internal logic preserves the TIO value and direction for an additional 2.5 internal clock cycles after a DSP56309 hardware RESET signal is asserted. This insures that a valid RESET signal is generated when the TIO signal is used to reset the DSP56309. Watchdog Toggle (Mode 10) Bit Settings TC3 1 TC2 0 TC1 1 TC0 0 Mode 10 Mode Characteristics NAME Toggle Function Watchdog TIO Output Clock Internal Freescale Semiconductor, Inc... 9.4.4.2 In this mode, the timer toggles an external signal after preset period. Set the TE bit to clear the counter and enable the timer. The value to which the timer is to count is loaded into the TPCR. The counter is loaded with the TLR value on the first timer clock received from either the DSP56309 internal clock divided by two (CLK/2) or the prescaler clock output. Each subsequent timer clock increments the counter. The TIO signal is set to the value of the INV bit. When the counter equals the value in the TCPR, the TCF bit in the TCSR is set, and a compare interrupt is generated if the TCIE bit is also set. If the TRM bit is set, the counter is loaded with the TLR value on the next timer clock and the count is resumed. If the TRM bit is cleared, the counter continues to be incremented on each subsequent timer clock. When counter overflow has occurred, the polarity of the TIO output signal is inverted, the TOF bit in the TCSR is set, and an overflow interrupt is generated if the TOIE bit is also set. The TIO polarity is determined by the INV bit. The counter is reloaded whenever the TLR is written with a new value while the TE bit is set. This process is repeated until the timer is disabled by clearing the TE bit. The counter contents can be read at any time by reading the TCR register. 9-26 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Triple Timer Module Timer Operational Modes Note: In this mode, internal logic preserves the TIO value and direction for an additional 2.5 internal clock cycles after a DSP56309 hardware RESET signal is asserted. This insures that a valid reset signal is generated when the TIO signal is used to reset the DSP56309. 9.4.5 Reserved Modes Modes 8, 11, 12, 13, 14, and 15 are reserved. Freescale Semiconductor, Inc... 9.4.6 Special Cases The following special cases apply during wait and stop state. 9.4.6.1 Timer Behavior during Wait Timer clocks are active during the execution of the WAIT instruction and timer activity is undisturbed. If a timer interrupt is generated, the DSP56309 leaves the wait state and services the interrupt. 9.4.6.2 Timer Behavior during Stop During the execution of the STOP instruction, the timer clocks are disabled, timer activity is stopped, and the TIO signals are disconnected. Any external changes that happen to the TIO signals are ignored when the DSP56309 is in the stop state. To insure correct operation, the timers should be disabled before the DSP56309 is placed into the stop state. 9.4.7 DMA Trigger Each timer can also be used to trigger DMA transfers. For this to occur, a DMA channel must be programmed to be triggered by a timer event. The timer issues a DMA trigger on every event in all modes of operation. The DMA channel does not have the capability to save multiple DMA triggers generated by the timer. To insure that all DMA triggers are serviced, the user must provide for the preceding DMA trigger to be serviced before the next trigger is received by the DMA channel. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 9-27 Freescale Semiconductor, Inc. Triple Timer Module Timer Operational Modes Freescale Semiconductor, Inc... 9-28 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. SECTION 10 ON-CHIP EMULATION MODULE Freescale Semiconductor, Inc... MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 10-1 Freescale Semiconductor, Inc. On-Chip Emulation Module Freescale Semiconductor, Inc... 10.1 10.2 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.11 10.12 10.13 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 ONCE MODULE SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 ONCE CONTROLLER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 ONCE MEMORY BREAKPOINT LOGIC. . . . . . . . . . . . . . . 10-9 ONCE TRACE LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15 METHODS OF ENTERING DEBUG MODE . . . . . . . . . . . 10-16 PIPELINE INFORMATION AND OGDB REGISTER. . . . . 10-18 DEBUGGING RESOURCES . . . . . . . . . . . . . . . . . . . . . . . 10-20 SERIAL PROTOCOL DESCRIPTION . . . . . . . . . . . . . . . . 10-22 TARGET SITE DEBUG SYSTEM REQUIREMENTS . . . . 10-23 ONCE MODULE EXAMPLES . . . . . . . . . . . . . . . . . . . . . . 10-23 JTAG PORT/ONCE MODULE INTERACTION . . . . . . . . . 10-29 10-2 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. On-Chip Emulation Module Introduction 10.1 INTRODUCTION Freescale Semiconductor, Inc... The DSP56300 core On-Chip Emulation (OnCE) module provides a means of interacting with the DSP56300 core and its peripherals nonintrusively so that a user can examine registers, memory, or on-chip peripherals, thus facilitating hardware and software development on the DSP56300 core processor. To achieve this, special circuits and dedicated signals on the DSP56300 core are defined to avoid sacrificing any user-accessible on-chip resource. The OnCE module resources can be accessed only after executing the JTAG instruction ENABLE_ONCE. These resources are accessible even when the chip is operating in normal mode. See Section 11NJTAG Port for a description of the JTAG functionality and its relation to the OnCE module. Figure 10-1 shows the block diagram of the OnCE module. PDB PIL GDB Pipeline Information Trace Logic TCK Control Bus TDI OnCE Controller TDO TRST DE XAB YAB PAB Trace Buffer Tags Buffer Breakpoint Logic AA0702 Figure 10-1 OnCE Module Block Diagram 10.2 OnCE MODULE SIGNALS The OnCE module controller functionality is accessed through the JTAG port. There are no dedicated OnCE module signals for the clock, data in, or data out. The JTAG signals TCK, TDI, and TDO are used to shift in and out data and instructions. See Section 11.2NJTAG Signals on page 11-4 for the description of the JTAG signals. To facilitate emulation-specific functions, one additional signal, called DE, is provided on the DSP56309. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 10-3 Freescale Semiconductor, Inc. On-Chip Emulation Module Debug Event (DE) 10.3 DEBUG EVENT (DE) Freescale Semiconductor, Inc... The bidirectional open drain debug event signal (DE) provides a fast means of entering debug mode from an external command controller (when input), and a fast means of acknowledging the entering of debug mode to an external command controller (when output). The assertion of this signal by a command controller causes the DSP56300 core to finish the current instruction being executed, save the instruction pipeline information, enter debug mode, and wait for commands to be entered from the TDI line. If the DE signal is used to enter debug mode, then it must be deasserted after the OnCE port responds with an acknowledge and before sending the first OnCE command. The assertion of this signal by the DSP56300 core indicates that the DSP has entered debug mode and is waiting for commands to be entered from the TDI line. The DE signal also facilitates multiple processor connections, as shown in Figure 10-2. DE TDI TDI TDO TDI TDO TDI TDO TDO TMS TCK TRST AA0703 Figure 10-2 OnCE Module Multiprocessor Configuration In this way, the user can stop all the devices in the system when one of the devices enters debug mode. The user can also stop all the devices synchronously by asserting the DE line. 10.4 OnCE CONTROLLER The OnCE controller contains the following blocks: OnCE Command Register (OCR), OnCE Decoder, and the status/control register. Figure 10-3 illustrates a block diagram of the OnCE controller. 10-4 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. On-Chip Emulation Module OnCE Controller OnCE Command Register TDI TCK ISBKPT Update ISTRACE ISDR ISSWDBG Status and Control Register TDO OnCE Decoder ISDEBUG Freescale Semiconductor, Inc... Register Read Register Write Mode Select AA0704 Figure 10-3 OnCE Controller Block Diagram 10.4.1 OnCE Command Register (OCR) The OCR is an 8-bit shift register that receives its serial data from the TDI signal. It holds the 8-bit commands to be used as input for the OnCE decoder. The OCR is shown in Figure 10-4. OCR OnCE Command Register Reset = $00 Write Only 7 R/W 6 GO 5 EX 4 3 2 1 0 RS4 RS3 RS2 RS1 RS0 AA0106 Figure 10-4 OnCE Command Register 10.4.1.1 Register Select (RS4RS0) Bits 04 The register select bits define which register is source/destination for the read/write operation. See Table 10-4 for the OnCE register select encoding. 10.4.1.2 Exit Command (EX) Bit 5 If the EX bit is set, leave debug mode and resume normal operation. The EXIT command is executed only if the GO command is issued, and the operation is write to OPDBR or MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 10-5 Freescale Semiconductor, Inc. On-Chip Emulation Module OnCE Controller read/write to ONo Register SelectedO. Otherwise the EX bit is ignored. Table 10-1 shows the definition of the EX bit. Table 10-1 EX Bit Definition EX 0 1 Action Remain in Debug mode Leave Debug mode Freescale Semiconductor, Inc... 10.4.1.3 GO Command (GO) Bit 6 If the GO bit is set, execute the instruction that resides in the PIL register. To execute the instruction, the core leaves debug mode. The core returns to debug mode immediately after executing the instruction if the EX bit is cleared. The core goes on to normal operation if the EX bit is set. The GO command is executed only if the operation is write to OPDBR or read/write to ONo Register SelectedO. Otherwise the GO bit is ignored. Table 10-2 shows the definition of the GO bit. Table 10-2 GO Bit Definition GO 0 1 Action InactiveNno action taken Execute instruction in PIL 10.4.1.4 Read/Write Command (R/W) Bit 7 The R/W bit, as shown in Table 10-3, specifies the direction of data transfer. Table 10-4 shows how to encode OnCE register selections. Table 10-3 R/W Bit Definition R/W 0 1 Action Write the data associated with the command into the register specified by RS4RS0. Read the data contained in the register specified by RS4RS0. Table 10-4 OnCE Register Select Encoding RS[4:0] 00000 Register Selected OnCE Status and Control Register (OSCR) 10-6 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. On-Chip Emulation Module OnCE Controller Table 10-4 OnCE Register Select Encoding (Continued) RS[4:0] 00001 00010 00011 00100 Register Selected Memory Breakpoint Counter (OMBC) Breakpoint Control Register (OBCR) Reserved Address Reserved Address Memory Limit Register 0 (OMLR0) Memory Limit Register 1 (OMLR1) Reserved Address Reserved Address GDB Register (OGDBR) PDB Register (OPDBR) PIL Register (OPILR) PDB GO-TO Register (for GO TO command) Trace Counter (OTC) Reserved Address PAB Register for Fetch (OPABFR) PAB Register for Decode (OPABDR) PAB Register for Execute (OPABEX) Trace Buffer and Increment Pointer Reserved Address Reserved Address Reserved Address Reserved Address Reserved Address No Register Selected Freescale Semiconductor, Inc... 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 101xx 11xx0 11x0x 110xx 11111 MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 10-7 Freescale Semiconductor, Inc. On-Chip Emulation Module OnCE Controller 10.4.2 OnCE Decoder (ODEC) The ODEC supervises the entire OnCE module activity. It receives as input the 8-bit command from the OCR, a signal from JTAG Controller (indicating that 8 or 24 bits have been received and update of the selected data register must be performed), and a signal indicating that the core was halted. The ODEC generates all the strobes required for reading and writing the selected OnCE registers. 10.4.3 OnCE Status and Control Register (OSCR) Freescale Semiconductor, Inc... The OSCR is a 24-bit register used to enable trace mode and to indicate the cause of entering debug mode. The control bits are read/write while the status bits are read-only. The OSCR bits are cleared by a hardware RESET signal. The OSCR is shown in Figure 10-5. 23 9 8 7 6 5 4 3 2 1 0 OnCE Status and Control Register Read/Write OS1 OS0 TO MBO SWO IME TME Indicates reserved bits, written as 0 for future compatibility AA0705 Figure 10-5 OnCE Status and Control Register (OSCR) 10.4.3.1 Trace Mode Enable (TME) Bit 0 The TME control bit, when set, enables trace mode. 10.4.3.2 Interrupt Mode Enable (IME) Bit 1 The IME control bit, when set, causes the chip to execute a vectored interrupt to the address VBA:$06 instead of entering debug mode. 10.4.3.3 Software Debug Occurrence (SWO) Bit 2 The SWO bit is a read-only status bit that is set when debug mode is entered because of the execution of the DEBUG or DEBUGcc instruction with condition true. This bit is cleared when leaving debug mode. 10.4.3.4 Memory Breakpoint Occurrence (MBO) Bit 3 The MBO bit is a read-only status bit that is set when debug mode is entered because a memory breakpoint has been encountered. This bit is cleared when leaving debug mode. 10-8 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. On-Chip Emulation Module OnCE Memory Breakpoint Logic 10.4.3.5 Trace Occurrence (TO) Bit 4 The TO bit is a read-only status bit that is set when debug mode is entered when the trace counter is zero while trace mode is enabled. This bit is cleared when leaving debug mode. 10.4.3.6 Reserved OCSR Bit 5 Bit 5 is reserved for future use. It is read as 0 and should be written with 0 for future compatibility. 10.4.3.7 Core Status (OS0, OS1) Bits 6-7 The OS0, OS1 bits are read-only status bits that provide core status information. By examining the status bits, the user can determine whether the chip has entered debug mode. Examining SWO, MBO, and TO identifies the cause of entering debug mode. The user can also examine these bits and determine the cause why the chip has not entered debug mode after debug event (DE) assertion or as a result of the execution of the JTAG debug request instruction (core waiting for the bus, STOP or WAIT instruction, etc.). These bits are also reflected in the JTAG instruction shift register, which allows the polling of the core status information at the JTAG level. This is useful when the DSP56300 core executes the STOP instruction (and therefore there are no clocks) to allow the reading of OSCR. See Table 10-5 for the definition of the OS0OS1 bits. Table 10-5 Core Status Bits Description OS1 0 0 1 1 OS0 0 1 0 1 Description DSP56300 core is executing instructions DSP56300 core is in wait or stop DSP56300 core is waiting for bus DSP56300 core is in debug mode Freescale Semiconductor, Inc... 10.4.3.8 Reserved Bits 8-23 Bits 823 are reserved for future use. They are read as 0 and should be written with 0 for future compatibility. 10.5 OnCE MEMORY BREAKPOINT LOGIC Memory breakpoints can be set on program memory or data memory locations. In addition, the breakpoint does not have to be in a specific memory address, but within an approximate address range where the program may be executing. This significantly increases the programmerOs ability to monitor what the program is doing in real time. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 10-9 Freescale Semiconductor, Inc. On-Chip Emulation Module OnCE Memory Breakpoint Logic The breakpoint logic, described in Figure 10-6, contains a latch for the addresses, which are registers that store the upper and lower address limit, address comparators, and a breakpoint counter. TCK TDO TDI PAB XAB YAB Memory Address Latch Memory Bus Select N,V TDI TCK TDO Freescale Semiconductor, Inc... Address Comparator 0 Breakpoint Control Memory Limit Register 0 N,V Memory Breakpoint Selection Address Comparator 1 Memory Limit Register 1 DEC Breakpoint Occurred Breakpoint Counter Count = 0 ISBKPT AA0706 Figure 10-6 OnCE Memory Breakpoint Logic 0 Address comparators are useful in determining where a program may be getting lost or when data is being written where it should not be written. They are also useful in halting a program at a specific point to examine/change registers or memory. Using address comparators to set breakpoints enables the user to set breakpoints in RAM or ROM and while in any operating mode. Memory accesses are monitored according to the contents of the OBCR as specified in Section 10.5.6NOnCE Breakpoint Control Register (OBCR). 10-10 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. On-Chip Emulation Module OnCE Memory Breakpoint Logic 10.5.1 OnCE Memory Address Latch (OMAL) The OMAL is a 16-bit register that latches the PAB, XAB or YAB on every instruction cycle according to the MBS1MBS0 bits in OBCR. 10.5.2 OnCE Memory Limit Register 0 (OMLR0) Freescale Semiconductor, Inc... The OMLR0 is a 16-bit register that stores the memory breakpoint limit. OMLR0 can be read or written through the JTAG port. Before enabling breakpoints, OMLR0 must be loaded by the external command controller. 10.5.3 OnCE Memory Address Comparator 0 (OMAC0) The OMAC0 compares the current memory address (stored in OMAL0) with the OMLR0 contents. 10.5.4 OnCE Memory Limit Register 1 (OMLR1) The OMLR1 is a 16-bit register that stores the memory breakpoint limit. OMLR1 can be read or written through the JTAG port. Before enabling breakpoints, OMLR1 must be loaded by the external command controller. 10.5.5 OnCE Memory Address Comparator 1 (OMAC1) The OMAC1 compares the current memory address (stored in OMAL0) with the OMLR1 contents. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 10-11 Freescale Semiconductor, Inc. On-Chip Emulation Module OnCE Memory Breakpoint Logic 10.5.6 OnCE Breakpoint Control Register (OBCR) The OBCR is a 16-bit register used to define the memory breakpoint events. OBCR can be read or written through the JTAG port. All the bits of the OBCR are cleared by a hardware RESET signal. The OBCR appears in Figure 10-7. 15 14 13 12 11 10 9 CC 11 8 CC 10 7 RW 11 6 RW 10 5 CC 01 4 CC 00 3 RW 01 2 RW 00 1 MB S1 0 MB S0 OnCE Breakpoint Control Register Reset = $0010 Read/Write * * * * BT1 BT0 Freescale Semiconductor, Inc... * Indicates reserved bits, written as 0 for future compatibility AA0707 Figure 10-7 OnCE Breakpoint Control Register (OBCR) Memory Breakpoint Select (MBS0MBS1) Bits 01 The MBS0MBS1 bits enable memory breakpoints 0 and 1, allowing them to occur when a memory access is performed on P, X, or Y space. See Table 10-6 for the definition of the MBS0MBS1 bits. Table 10-6 Memory Breakpoint 0 and 1 Select Table MBS1 0 0 1 1 MBS0 0 1 0 1 Reserved Breakpoint on P access Breakpoint on X access Breakpoint on Y access Description 10.5.6.1 Breakpoint 0 Read/Write Select (RW00RW01) Bits 23 The RW00RW01 bits define the memory breakpoint 0 to occur when a memory address access is performed for read, write, or both. See Table 10-7 for the definition of the RW00RW01 bits. 10.5.6.2 10-12 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. On-Chip Emulation Module OnCE Memory Breakpoint Logic Table 10-7 Breakpoint 0 Read/Write Select Table RW01 0 0 1 1 RW00 0 1 0 1 Breakpoint disabled Breakpoint on write access Breakpoint on read access Breakpoint on read or write access Description Freescale Semiconductor, Inc... 10.5.6.3 Breakpoint 0 Condition Code Select (CC00CC01) Bits 45 The CC00CC01 bits define the condition of the comparison between the current memory address (OMAL0) and the memory limit register 0 (OMLR0). See Table 10-8 for the definition of the CC00CC01 bits. Table 10-8 Breakpoint 0 Condition Select Table CC01 0 0 1 1 CC00 0 1 0 1 Breakpoint on not equal Breakpoint on equal Breakpoint on less than Breakpoint on greater than Description Breakpoint 1 Read/Write Select (RW10RW11) Bits 67 The RW10RW11 bits control define memory breakpoint 1 to occur when a memory address access is performed for read, write, or both. See Table 10-9 for the definition of the RW10RW11 bits. Table 10-9 Breakpoint 1 Read/Write Select Table RW11 0 0 1 1 RW10 0 1 0 1 Breakpoint disabled Breakpoint on write access Breakpoint on read access Breakpoint read or write access Description 10.5.6.4 MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 10-13 Freescale Semiconductor, Inc. On-Chip Emulation Module OnCE Memory Breakpoint Logic 10.5.6.5 Breakpoint 1 Condition Code Select (CC10CC11) Bits 89 The CC10CC11 bits define the condition of the comparison between the current memory address (OMAL0) and the OnCE Memory Limit Register 1 (OMLR1). See Table 10-10 for the definition of the CC10CC11 bits. Table 10-10 Breakpoint 1 Condition Select Table CC11 0 CC10 0 1 0 1 Breakpoint on not equal Breakpoint on equal Breakpoint on less than Breakpoint on greater than Description Freescale Semiconductor, Inc... 0 1 1 Breakpoint 0 and 1 Event Select (BT0BT1) Bits 1011 The BT0BT1 bits define the sequence between breakpoint 0 and 1. If the condition defined by BT0BT1 is met, then the OnCE Breakpoint Counter (OMBC) is decremented. See Table 10-11 for the definition of the BT0BT1 bits. Table 10-11 Breakpoint 0 and 1 Event Select Table BT1 0 0 1 1 BT0 0 1 0 1 Description Breakpoint 0 and Breakpoint 1 Breakpoint 0 or Breakpoint 1 Breakpoint 1 after Breakpoint 0 Breakpoint 0 after Breakpoint 1 10.5.6.6 10.5.6.7 OnCE Memory Breakpoint Counter (OMBC) The OMBC is a 16-bit counter that is loaded with a value equal to the number of times minus one that a memory access event should occur before a memory breakpoint is declared. The memory access event is specified by the OBCR and by the memory limit registers. On each occurrence of the memory access event, the breakpoint counter is decremented. When the counter reaches 0 and a new occurrence takes place, the chip enters debug mode. The OMBC can be read or written through the JTAG port. Every time that the limit register is changed or a different breakpoint event is selected in the OBCR, the breakpoint counter must be written afterwards. This insures that the OnCE 10-14 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. On-Chip Emulation Module OnCE Trace Logic breakpoint logic is reset and that no previous events can affect the new breakpoint event selected. The breakpoint counter is cleared by a hardware RESET signal. 10.5.6.8 Reserved Bits 12-15 Bits 1215 are reserved for future use. They are read as 0 and should be written with 0 for future compatibility. 10.6 OnCE TRACE LOGIC Freescale Semiconductor, Inc... Using the OnCE trace logic, execution of instructions in single or multiple steps is possible. The OnCE trace logic causes the chip to enter debug mode after the execution of one or more instructions and wait for OnCE commands from the debug serial port. The OnCE trace logic block diagram is shown in Figure 10-8. End of Instruction TDI TDO TCK Count = 0 Trace Counter DEC ISTRACE AA0708 Figure 10-8 OnCE Trace Logic Block Diagram Trace mode has a counter associated with it so that more than one instruction can be executed before returning back to debug mode. The objective of the counter is to allow the user to take multiple instruction steps real time before entering debug mode. This feature helps the software developer debug sections of code that do not have a normal flow or are getting hung up in infinite loops. The OTC also enables the user to count the number of instructions executed in a code segment. To enable trace mode, the counter is loaded with a value, the program counter is set to the start location of the instruction(s) to be executed real time, the TME bit is set in the MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 10-15 Freescale Semiconductor, Inc. On-Chip Emulation Module Methods of Entering Debug Mode OSCR, and the DSP56300 core exits debug mode by executing the appropriate command issued by the external command controller. Upon exiting debug mode, the counter is decremented after each execution of an instruction. Interrupts are serviceable then. Moreover, all executed instructions, including fast interrupt services and the execution of each repeated instruction, cause the OTC to be decremented. Upon decrementing to 0, the DSP56300 core reenters debug mode, the trace occurrence bit (TO) in the OSCR register is set, the core status bits OS[1:0] are set to 11, and the DE signal is asserted to indicate that the DSP56300 core has entered debug mode and is requesting service. Freescale Semiconductor, Inc... The OnCE Trace Counter (OTC) is a 16-bit counter that can be read or written through the JTAG port. If N instructions are to be executed before entering debug mode, the OTC should be loaded with N 1. The OTC is cleared by a hardware RESET signal. 10.7 METHODS OF ENTERING DEBUG MODE Entering debug mode is acknowledged by the chip by setting the core status bits OS1 and OS0 and asserting the DE line. This informs the external command controller that the chip has entered debug mode and is waiting for commands. The DSP56300 core can disable the OnCE module if the ROM Security option is implemented. If the ROM security is implemented, the OnCE module remains inactive until a write operation to the OGDBR is executed by the DSP56300 core. 10.7.1 External Debug Request During RESET Assertion Holding the DE line asserted during the assertion of RESET causes the chip to enter debug mode. After receiving the acknowledge, the external command controller must negate the DE line before sending the first command. Note: In this case, the chip does not execute any instruction before entering debug mode. 10.7.2 External Debug Request During Normal Activity Holding the DE line asserted during normal chip activity causes the chip to finish the execution of the current instruction and then enter Debug mode. After receiving the acknowledge, the external command controller must negate the DE line before sending 10-16 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. On-Chip Emulation Module Methods of Entering Debug Mode the first command. This process is the same for any newly fetched instruction, including instructions fetched by the interrupt processing or instructions that will be aborted by the interrupt processing. Note: In this case the chip completes the execution of the current instruction and stops after the newly fetched instruction enters the instruction latch. 10.7.3 Executing the JTAG DEBUG_REQUEST Instruction Freescale Semiconductor, Inc... Executing the JTAG instruction DEBUG_REQUEST asserts an internal debug request signal. Consequently, the chip finishes the execution of the current instruction and stops after the newly fetched instruction enters the instruction latch. After entering debug mode, the core status bits OS1 and OS0 are set and the DE line is asserted, thus acknowledging the external command controller that debug mode has been entered. 10.7.4 External Debug Request During Stop Executing the JTAG instruction DEBUG_REQUEST (or asserting DE) while the chip is in the stop state (i. e., has executed a STOP instruction) causes the chip to exit the stop state and enter debug mode. After receiving the acknowledge, the external command controller must negate DE before sending the first command. Note: In this case, the chip completes the execution of the STOP instruction and halts after the next instruction enters the instruction latch. 10.7.5 External Debug Request During Wait Executing the JTAG instruction DEBUG_REQUEST (or asserting DE) while the chip is in the wait state (i. e., has executed a WAIT instruction) causes the chip to exit the wait state and enter debug mode. After receiving the acknowledge, the external command controller must negate DE before sending the first command. Note: In this case, the chip completes the execution of the WAIT instruction and halts after the next instruction enters the instruction latch. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 10-17 Freescale Semiconductor, Inc. On-Chip Emulation Module Pipeline Information and OGDB Register 10.7.6 Software Request During Normal Activity Upon executing the DSP56300 core instruction DEBUG (or DEBUGcc when the specified condition is true), the chip enters debug mode after the instruction following the DEBUG instruction has entered the instruction latch. 10.7.7 Enabling Trace Mode Freescale Semiconductor, Inc... When Trace mode is enabled and the OTC is greater than zero, the OTC is decremented after each instruction execution. Execution of an instruction when the value in the OTC is 0 causes the chip to enter debug mode after completing the execution of the instruction. Only instructions actually executed cause the OTC to decrement. An aborted instruction does not decrement the OTC and does not cause the chip to enter debug mode. 10.7.8 Enabling Memory Breakpoints When the memory breakpoint mechanism is enabled with a breakpoint counter value of 0, the chip enters debug mode after completing the execution of the instruction that caused the memory breakpoint to occur. In case of breakpoints on executed program memory fetches, the breakpoint is acknowledged immediately after the execution of the fetched instruction. In case of breakpoints on accesses to X, Y or program memory spaces by MOVE instructions, the breakpoint is acknowledged after the completion of the instruction following the instruction that accessed the specified address. 10.8 PIPELINE INFORMATION AND OGDB REGISTER To restore the pipeline and to resume normal chip activity upon returning from debug mode, a number of on-chip registers store the chip pipeline status. Figure 10-9 shows the block diagram of the pipeline information registers, with the exception of the PAB registers, which appear in Figure 10-10 on page 10-22. 10-18 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. On-Chip Emulation Module Pipeline Information and OGDB Register GDB Register (OGDBR) GDB PDB Register (OPDBR) TDI PDB PIL Register (OPILR) Freescale Semiconductor, Inc... TDO TCK PIL AA0709 Figure 10-9 OnCE Pipeline Information and GDB Registers 10.8.1 OnCE PDB Register (OPDBR) The OPDBR is a 24-bit latch that stores the value of the program data bus generated by the last program memory access of the core before debug mode is entered. The OPDBR register can be read or written through the JTAG port. This register is affected by the operations performed during debug mode and must be restored by the external command controller when returning to normal mode. 10.8.2 OnCE PIL Register (OPILR) The OPILR is a 24-bit latch that stores the value of the instruction latch before debug mode is entered. OPILR can only be read through the JTAG port. Note: Since the instruction latch is affected by the operations performed during debug mode, it must be restored by the external command controller when returning to normal mode. Since there is no direct write access to the instruction latch, the task of restoring is accomplished by writing to OPDBR with no-GO and no-EX. In this case the data written on PDB is transferred into the instruction latch. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 10-19 Freescale Semiconductor, Inc. On-Chip Emulation Module Debugging Resources 10.8.3 OnCE GDB Register (OGDBR) The OGDBR is a 16-bit latch that can only be read through the JTAG port. The OGDBR is not actually required for restoring the pipeline status but is required as a means of passing information between the chip and the external command controller. The OGDBR is mapped on the X internal I/O space at address $FFFC. Whenever the external command controller needs the contents of a register or memory location, it forces the chip to execute an instruction that brings that information to the OGDBR. Then the contents of the OGDBR are delivered serially to the external command controller by the command READ GDB REGISTER. Freescale Semiconductor, Inc... 10.9 DEBUGGING RESOURCES To ease debugging activity and keep track of program flow, the DSP56300 core provides a number of on-chip dedicated resources. There are three read-only PAB registers that give pipeline information when debug mode is entered, and a trace buffer that stores the address of the last instruction that was executed, as well as the addresses of the last 12 change-of-flow instructions. 10.9.1 OnCE PAB Register for Fetch (OPABFR) The OPABFR is a 16-bit register that stores the address of the last instruction whose fetch was started before debug mode was entered. The OPABFR can only be read through the JTAG port. This register is not affected by the operations performed during debug mode. 10.9.2 PAB Register for Decode (OPABDR) The OPABDR is a 16-bit register that stores the address of the instruction currently on the PDB. This is the instruction whose fetch was completed before the chip has entered debug mode. The OPABDR can only be read through the JTAG port. This register is not affected by the operations performed during debug mode. 10.9.3 OnCE PAB Register for Execute (OPABEX) The OPABEX is a 16-bit register that stores the address of the instruction currently in the instruction latch. This is the instruction that would have been decoded and executed if 10-20 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. On-Chip Emulation Module Debugging Resources the chip would not have entered debug mode. The OPABEX register can only be read through the JTAG port. This register is not affected by the operations performed during debug mode. 10.9.4 Trace Buffer Freescale Semiconductor, Inc... The trace buffer stores the addresses of the last 12 change-of-flow instructions that were executed, as well as the address of the last executed instruction. The trace buffer is implemented as a circular buffer containing 12 17-bit registers and one 4-bit counter. All the registers have the same address, but any read access to the trace buffer address causes the counter to increment, thus pointing to the next trace buffer register. The registers are serially available to the external command controller through their common trace buffer address. Figure 10-10 on page 10-22 shows the block diagram of the trace buffer. The trace buffer is not affected by the operations performed during debug mode except for the trace buffer pointer increment when reading the trace buffer. When entering debug mode, the trace buffer counter is pointing to the trace buffer register containing the address of the last executed instructions. The first trace buffer read obtains the oldest address and the following trace buffer reads get the other addresses from the oldest to the newest, in order of execution. Notes: 1. To insure trace buffer coherence, a complete set of 12 reads of the Trace buffer must be performed. This is necessary due to the fact that each read increments the trace buffer pointer, thus pointing to the next location. After 12 reads, the pointer indicates the same location as before starting the read procedure. 2. On any change of flow instruction, the trace buffer stores both the address of the change of flow instruction, as well as the address of the target of the change of flow instruction. In the case of conditional change of flows, the address of the change of flow instruction is always stored (regardless of the fact that the change of flow is true or false), but if the conditional change of flow is false (i.e., not taken) the address of the target is not stored. In order to facilitate the program trace reconstruction, every trace buffer location has an additional Oinvalid bitO (bit 24). If a conditional change of flow instruction has a Ocondition falseO, the invalid bit is set, thus marking this instruction as not taken. Therefore, it is imperative to read 17 bits of data when reading the 12 trace buffer registers. Since data is read LSB first, the invalid bit is the first bit to be read. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 10-21 Freescale Semiconductor, Inc. On-Chip Emulation Module Serial Protocol Description PAB Fetch Address (OPABFR) Decode Address (OPABDR) Freescale Semiconductor, Inc... Execute Address (OPABEX) Trace Buffer Register 0 Trace Buffer Register 1 Circular Buffer Pointer Trace Buffer Register 2 Trace Buffer Register 11 TDI Trace Buffer Shift Register TCK TDO AA0710 Figure 10-10 OnCE Trace Buffer 10.10 SERIAL PROTOCOL DESCRIPTION To permit an efficient means of communication between the external command controller and the DSP56300 core chip, the following protocol is adopted. Before starting any debugging activity, the external command controller has to wait for an acknowledge 10-22 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. On-Chip Emulation Module Target Site Debug System Requirements on the DE line indicating that the chip has entered debug mode. Optionally the external command controller can poll the OS1 and OS0 bits in the JTAG instruction shift register. The external command controller communicates with the chip by sending 8-bit commands that can be accompanied by 24 bits of data. Both commands and data are sent or received LSB first. After sending a command, the external command controller should wait for the DSP56300 core chip to acknowledge execution of the command. The external command controller can send a new command only after the chip has acknowledged execution of the previous command. The OnCE commands are classified as follows: Freescale Semiconductor, Inc... Read commands (when the chip delivers the required data) Write commands (when the chip receives data and writes the data in one of the OnCE registers) Commands that do not have data transfers associated with them The commands are 8 bits long. The command formats are shown in Figure 10-4 on page 10-5. 10.11 TARGET SITE DEBUG SYSTEM REQUIREMENTS A typical debug environment consists of a target system where the DSP56300 core-based device resides in the user defined hardware. The JTAG port interfaces to the external command controller over a 8-wire link consisting of the five JTAG port wires, one OnCE module wire, a ground, and a reset wire. The reset wire is optional and is only used to reset the DSP56300 core-based device and its associated circuitry. The external command controller acts as the medium between the DSP56300 core target system and a host computer. The external command controller circuit acts as a JTAG port driver and host computer command interpreter. The controller issues commands based on the host computer inputs from a user interface program that communicates with the user. 10.12 OnCE MODULE EXAMPLES Following are some examples of debugging procedures. All these examples assume that the DSP is the only device in the JTAG chain. If there is more than one device in the chain (additional DSPs or other devices), the other devices can be forced to execute the JTAG BYPASS instruction such as their effect in the serial stream will be one bit per additional MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 10-23 Freescale Semiconductor, Inc. On-Chip Emulation Module OnCE Module Examples device. The events such as select-DR, select-IR, update-DR, and shift-DR refer to bringing the JTAG TAP in the corresponding state. For a detailed description of the JTAG protocol, see Section 11NJTAG Port. 10.12.1 Checking Whether the Chip Has Entered Debug Mode There are two methods to verify that the chip has entered debug mode: Every time the chip enters debug mode, a pulse is generated on the DE signal. A pulse is also generated every time the chip acknowledges the execution of an instruction while in debug mode. An external command controller can connect the DE line to an interrupt signal in order to sense the acknowledge. An external command controller can poll the JTAG instruction shift register for the status bits OS[1:0]. When the chip is in Debug mode, these bits are set to the value 11. Note: In the following paragraphs, the ACK notation denotes the operation performed by the command controller to check whether debug mode has been entered (either by sensing DE or by polling JTAG instruction shift register). Freescale Semiconductor, Inc... 10.12.2 Polling the JTAG Instruction Shift Register In order to poll the core status bits in the JTAG instruction shift register the following sequence must be performed: 1. Select shift-IR. Passing through capture-IR loads the core status bits into the instruction shift register. 2. Shift in ENABLE_ONCE. While shifting-in the new instruction, the captured status information is shifted-out. Pass through update-IR. 3. Return to Run-Test/Idle. The external command controller can analyze the information shifted out and detect whether the chip has entered debug mode. 10-24 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. On-Chip Emulation Module OnCE Module Examples 10.12.3 Saving Pipeline Information The debugging activity is accomplished by means of DSP56300 core instructions supplied from the external command controller. Therefore, the current state of the DSP56300 core pipeline must be saved prior to starting the debug activity and the state must be restored prior to returning to normal mode. Here is the description of the save procedure (it assumes that ENABLE_ONCE has been executed and Debug mode has been entered and verified, as described in Section 10.12.1NChecking Whether the Chip Has Entered Debug Mode): Freescale Semiconductor, Inc... 1. Select shift-DR. Shift in the ORead PDBO. Pass through update-DR. 2. Select shift-DR. Shift out the 24 bit OPDB register. Pass through update-DR. 3. Select shift-DR. Shift in the ORead PILO. Pass through update-DR. 4. Select shift-DR. Shift out the 24 bit OPILR register. Pass through update-DR. Note that there is no need to verify acknowledge between steps 1 and 2, as well as 3 and 4, because completion is guaranteed by design. 10.12.4 Reading the Trace Buffer An optional step during debugging activity is reading the information associated with the trace buffer in order to enable an external program to reconstruct the full trace of the executed program. In the following description of the read trace buffer procedure, it is assumed that all actions described in Saving Pipeline Information have been executed. 1. Select shift-DR. Shift in the ORead PABFRO. Pass through update-DR. 2. Select shift-DR. Shift out the 16 bit OPABFR register. Pass through update-DR. 3. Select shift-DR. Shift in the ORead PABDRO. Pass through update-DR. 4. Select shift-DR. Shift out the 16 bit OPABDR register. Pass through update-DR. 5. Select shift-DR. Shift in the ORead PABEXO. Pass through update-DR. 6. Select shift-DR. Shift out the 16 bit OPABEX register. Pass through update-DR. 7. Select shift-DR. Shift in the ORead FIFOO. Pass through update-DR. 8. Select shift-DR. Shift out the 17 bit FIFO register. Pass through update-DR. 9. Repeat steps 7 and 8 for the entire FIFO (12 times). MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 10-25 Freescale Semiconductor, Inc. On-Chip Emulation Module OnCE Module Examples Note: The user must read the entire FIFO, since each read increments the FIFO pointer, thus pointing to the next FIFO location. At the end of this procedure, the FIFO pointer points back to the beginning of the FIFO. The information that has been read by the external command controller now contains the address of the newly fetched instruction, the address of the instruction currently on the PDB, the address of the instruction currently on the instruction latch, as well as the addresses of the last 12 instructions that have been executed and are change of flow. A user program can now reconstruct the flow of a full trace based on this information and on the original source code of the currently running program. Freescale Semiconductor, Inc... 10.12.5 Displaying a Specified Register To display a specified register, the DSP56300 must be in debug mode and all actions described in Section 10.12.3NSaving Pipeline Information have been executed. The sequence of actions is as follows: 1. Select shift-DR. Shift in the OWrite PDB with GO no-EXO. Pass through update-DR. 2. Select shift-DR. Shift in the 24-bit opcode: OMOVE reg, X:OGDBO. Pass through update-DR to actually write OPDBR and thus begin executing the MOVE instruction. 3. Wait for DSP to reenter debug mode (wait for DE or poll core status). 4. Select shift-DR and shift in OREAD GDB REGISTERO. Pass through update-DR. This step selects OGDBR as the data register for the read. 5. Select shift-DR. Shift out the OGDBR contents. Pass through update-DR. Wait for next command. 10.12.6 Displaying X Memory Area Starting at Address $xxxx The DSP56309 must be in debug mode and all actions described in Section 10.12.3NSaving Pipeline Information must have been executed. Since R0 is used as pointer for the memory, R0 is saved first. The sequence of actions is as follows: 1. Select shift-DR. Shift in the OWrite PDB with GO no-EXO. Pass through update-DR. 10-26 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. On-Chip Emulation Module OnCE Module Examples 2. Select shift-DR. Shift in the 24-bit opcode: OMOVE R0, X:OGDBO. Pass through update-DR to actually write OPDBR and thus begin executing the MOVE instruction. 3. Wait for DSP to reenter debug mode (wait for DE or poll core status). 4. Select shift-DR and shift in OREAD GDB REGISTERO. Pass through update-DR. (This selects OGDBR as the data register for read.) 5. Select shift-DR. Shift out the OGDBR contents. Pass through update-DR. R0 is now saved. Freescale Semiconductor, Inc... 6. Select shift-DR. Shift in the OWrite PDB with no-GO no-EXO. Pass through update-DR. 7. Select shift-DR. Shift in the 24 bit opcode: OMOVE #$xxxx,R0O. Pass through update-DR to actually write OPDBR. 8. Select shift-DR. Shift in the OWrite PDB with GO no-EXO. Pass through update-DR. 9. Select shift-DR. Shift in the second word of the 24 bit opcode: OMOVE #$xxxx,R0O (the $xxxx field). Pass through update-DR to actually write OPDBR and execute the instruction. R0 is loaded with the base address of the memory block to be read. 10. Wait for DSP to reenter debug mode. (Wait for DE or poll core status.) 11. Select shift-DR. Shift in the OWrite PDB with GO no-EXO. Pass through update-DR. 12. Select shift-DR. Shift in the 24-bit opcode: OMOVE X:(R0)+, X:OGDBO. Pass through update-DR to actually write OPDBR and thus begin executing the MOVE instruction. 13. Wait for DSP to reenter debug mode. (Wait for DE or poll core status.) 14. Select shift-DR and shift in OREAD GDB REGISTERO. Pass through update-DR. (This selects OGDBR as the data register for read.) 15. Select shift-DR. Shift out the OGDBR contents. Pass through update-DR. The memory contents of address $xxxx have been read. 16. Select shift-DR. Shift in the ONO SELECT with GO no-EXO. Pass through update-DR. This reexecutes the same OMOVE X:(R0)+, X:OGDBO instruction. 17. Repeat from step 14 to complete the reading of the entire block. When finished, restore the original value of R0. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 10-27 Freescale Semiconductor, Inc. On-Chip Emulation Module OnCE Module Examples 10.12.7 Returning from Debug to Normal Mode (Same Program) In this case, you have finished examining the current state of the machine, changed some of the registers, and wish to return and continue execution of the same program from the point where it stopped. Therefore, you must restore the pipeline of the machine and enable normal instruction execution. The sequence of actions to do so is listed below: 1. Select shift-DR. Shift in the OWrite PDB with no-GO no-EXO. Pass through update-DR. Freescale Semiconductor, Inc... 2. Select shift-DR. Shift in the 24 bits of saved PIL (instruction latch value). Pass through update-DR to actually write the instruction latch. 3. Select shift-DR. Shift in the OWrite PDB with GO and EXO. Pass through update-DR. 4. Select shift-DR. Shift in the 24 bits of saved PDB. Pass through update-DR to actually write the PDB. At the same time the internally saved value of the PAB is driven back from the PABFR register onto the PAB, the ODEC releases the chip from debug mode, and the normal flow of execution is continued. 10.12.8 Returning from Debug to Normal Mode (New Program) In this case, you have finished examining the current state of the machine, changed some of the registers, and wish to start the execution of a new program (the GOTO command). Therefore, you must force a Ochange-of-flowO to the starting address of the new program ($xxxx). The sequence of actions to do so is listed below: 1. Select shift-DR. Shift in the OWrite PDB with no-GO no-EXO. Pass through update-DR. 1. Select shift-DR. Shift in the 24-bit O$0AF080O which is the opcode of the JUMP instruction. Pass through update-DR to actually write the instruction latch. 2. Select shift-DR. Shift in the OWrite PDB-GO-TO with GO and EXO. Pass through update-DR. 3. Select shift-DR. Shift in the 16 bit of O$xxxxO. Pass through update-DR to actually write the PDB. At this time the ODEC releases the chip from debug mode and the execution is started from the address $xxxx. Note: If the device enters debug mode during a DO LOOP, REP instruction, or other special cases such as interrupt processing, STOP, WAIT, or conditional branching, you must first reset the DSP56300 and then proceed with the execution of the new program. 10-28 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. On-Chip Emulation Module JTAG PORT/onCE MODULE INTERACTION 10.13 JTAG PORT/OnCE MODULE INTERACTION This subsection lists the details of the JTAG port/OnCE module interaction and TMS sequencing required in order to achieve the communication described in Section 10.12NOnCE Module Examples. The external command controller can force the DSP56300 into debug mode by executing the JTAG instruction DEBUG_REQUEST. In order to check that the DSP56300 has entered debug mode, the external command controller must poll the status by reading the OS[1:0] bits in the JTAG instruction shift register. The TMS sequencing appears in Table 10-12. The sequence to enable the OnCE module appears in Table 10-13. After executing the JTAG instructions DEBUG_REQUEST and ENABLE_ONCE and after the core status was polled to verify that the chip is in debug mode, the pipeline saving procedure must take place. The TMS sequencing for this procedure is depicted in Table 10-12. Table 10-12 TMS Sequencing for DEBUG_REQUEST Step a b c d e TMS 0 1 1 0 0 JTAG Port Run-Test/Idle Select-DR-Scan Select-IR-Scan Capture-IR Shift-IR OnCE Module Idle Idle Idle Idle Idle Note N N N The status is sampled in the shifter. The four bits of the JTAG DEBUG_REQUEST (0111) are shifted in while status is shifted out. N The debug request is generated. N Freescale Semiconductor, Inc... .................................................................. e f g h i j 0 1 1 1 1 0 Shift-IR Exit1-IR Update-IR Select-DR-Scan Select-IR-Scan Capture-IR Idle Idle Idle Idle Idle Idle The status is sampled in the shifter. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 10-29 Freescale Semiconductor, Inc. On-Chip Emulation Module JTAG PORT/onCE MODULE INTERACTION Table 10-12 TMS Sequencing for DEBUG_REQUEST (Continued) Step k TMS 0 JTAG Port Shift-IR OnCE Module Idle Note The four bits of the JTAG DEBUG_REQUEST (0111) are shifted in while status is shifted out. .................................................................. k l 0 1 1 0 Shift-IR Exit1-IR Update-IR Run-Test/Idle ................................................ n 0 Run-Test/Idle Idle Idle Idle Idle Idle Freescale Semiconductor, Inc... m n This step is repeated, enabling an external command controller to poll the status. In Ostep nO the external command controller verifies that the OS[1:0] bits have the value 11, indicating that the chip has entered debug mode. If the chip has not yet entered debug mode, the external command controller goes to Ostep bO, Ostep cO etc. until debug mode is acknowledged. Table 10-13 TMS Sequencing for ENABLE_ONCE Step a b c d e f g h i j k TMS 1 0 1 1 0 0 0 0 0 1 1 JTAG Port Test-Logic-Reset Run-Test/Idle Select-DR-Scan Select-IR-Scan Capture-IR Shift-IR Shift-IR Shift-IR Shift-IR Exit1-IR Update-IR OnCE Module Idle Idle Idle Idle Idle Idle Idle Idle Idle Idle Idle N The OnCE module is enabled. Note N N N N The core status bits are captured. The four bits of the JTAG ENABLE_ONCE instruction (0110) are shifted into the JTAG instruction register while status is shifted out. 10-30 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. On-Chip Emulation Module JTAG PORT/onCE MODULE INTERACTION Table 10-13 TMS Sequencing for ENABLE_ONCE (Continued) Step l TMS 0 JTAG Port Run-Test/Idle ................................................ l 0 Run-Test/Idle Idle OnCE Module Idle Note This step can be repeated, enabling an external command controller to poll the status. Table 10-14 TMS Sequencing for Reading Pipeline Registers Freescale Semiconductor, Inc... Step a b c d TMS 0 1 0 0 JTAG Port Run-Test/Idle Select-DR-Scan Capture-DR Shift-DR OnCE Module Idle Idle Idle Idle Note N N N The eight bits of the OnCE command ORead PILO (10001011) are shifted in. .................................................................. d e f g h i 0 1 1 1 0 0 Shift-DR Exit1-DR Update-DR Select-DR-Scan Capture-DR Shift-DR Idle Idle Execute ORead PILO Idle Idle Idle N The PIL value is loaded in the shifter. N N The 24 bits of the PIL are shifted out (24 steps). .................................................................. i j k l m 0 1 1 1 0 Shift-DR Exit1-DR Update-DR Select-DR-Scan Capture-DR Idle Idle Idle Idle Idle N N N N MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 10-31 Freescale Semiconductor, Inc. On-Chip Emulation Module JTAG PORT/onCE MODULE INTERACTION Table 10-14 TMS Sequencing for Reading Pipeline Registers (Continued) Step n TMS 0 JTAG Port Shift-DR OnCE Module Idle Note The eight bits of the OnCE command ORead PDBO (10001010) are shifted in. .................................................................. n o p 0 1 1 1 0 0 Shift-DR Exit1-DR Update-DR Select-DR-Scan Capture-DR Shift-DR Idle Idle Execute ORead PDBO Idle Idle Idle N PDB value is loaded in shifter. N N The 24 bits of the PDB are shifted out (24 steps). Freescale Semiconductor, Inc... q r s .................................................................. s t u v 0 1 1 0 Shift-DR Exit1-DR Update-DR Run-Test/Idle ................................................ v 0 Run-Test/Idle Idle Idle Idle Idle Idle N N This step can be repeated, enabling an external command controller to analyze the information. During Ostep vO the external command controller stores the pipeline information. Afterwards, it can proceed with the debug activities as requested by the user. 10-32 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. SECTION 11 JTAG PORT Freescale Semiconductor, Inc... MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 11-1 Freescale Semiconductor, Inc. JTAG Port 11.1 11.2 11.3 11.4 11.5 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 JTAG SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 TAP CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 DSP56300 RESTRICTIONS . . . . . . . . . . . . . . . . . . . . . . . 11-12 DSP56309 BOUNDARY SCAN REGISTER . . . . . . . . . . . 11-13 Freescale Semiconductor, Inc... 11-2 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. JTAG Port Introduction 11.1 INTRODUCTION The DSP56300 core provides a dedicated user-accessible test access port (TAP) that is fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Problems associated with testing high density circuit boards have led to development of this proposed standard under the sponsorship of the Test Technology Committee of IEEE and the JTAG. The DSP56300 core implementation supports circuit-board test strategies based on this standard. The test logic includes a TAP that consists of five dedicated signals, a 16-state controller, and three test data registers. A Boundary Scan Register (BSR) links all device signals into a single shift register. The test logic, implemented utilizing static logic design, is independent of the device system logic. The DSP56300 core implementation provides the following capabilities: Performs boundary scan operations to test circuit-board electrical continuity (EXTEST) Bypasses the DSP56300 core for a given circuit-board test by effectively reducing the BSR to a single cell (BYPASS) Samples the DSP56300 core-based device system signals during operation and transparently shifts out the result in the BSR Preloads values to output signals prior to invoking the EXTEST instruction (SAMPLE/PRELOAD) Disables the output drive to signals during circuit-board testing (HI-Z) Provides a means of accessing the OnCE controller and circuits to control a target system (ENABLE_ONCE) Provides a means of entering debug Mode (DEBUG_REQUEST) Queries identification information (manufacturer, part number and version) from a DSP56300 core-based device (IDCODE) Forces test data onto the outputs of a DSP56300 core-based device while replacing its boundary scan register in the serial data path with a single bit register (CLAMP) This section, which includes aspects of the JTAG implementation that are specific to the DSP56300 core, is intended to be used with the supporting IEEE 1149.1 document. The discussion includes those items required by the standard to be defined and, in certain cases, provides additional information specific to the DSP56300 core implementation. For internal details and applications of the standard, refer to the IEEE 1149.1 document. Figure 11-1 shows a block diagram of the TAP port. Freescale Semiconductor, Inc... MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 11-3 Freescale Semiconductor, Inc. JTAG Port JTAG Signals Boundary Scan Register TDI Bypass ID Register Freescale Semiconductor, Inc... OnCE Logic Decoder 3 2 1 0 TDO MUX 4-Bit Instruction Register TMS TAP Ctrl AA0113 TCK TRST Figure 11-1 TAP Block Diagram 11.2 JTAG SIGNALS As described in the IEEE 1149.1 document, the JTAG port requires a minimum of four signals to support TDI, TDO, TCK, and TMS signals. The DSP56300 family also provides 11-4 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MUX MOTOROLA Freescale Semiconductor, Inc. JTAG Port JTAG Signals the optional TRST signal. On the DSP56309, the debug event (DE) signal is provided for use by the OnCE module; it is documented in Section 10NOn-Chip Emulation Module. The signal functions are described in the following paragraphs. 11.2.1 Test Clock (TCK) The TCK signal is used to synchronize the test logic. Freescale Semiconductor, Inc... 11.2.2 Test Mode Select (TMS) The TMS signal is used to sequence the test controllerOs state machine. The TMS is sampled on the rising edge of TCK, and it has an internal pull-up resistor. 11.2.3 Test Data Input (TDI) Serial test instruction and data are received through the Test Data Input (TDI) signal. TDI is sampled on the rising edge of TCK, and it has an internal pull-up resistor. 11.2.4 Test Data Output (TDO) The TDO signal is the serial output for test instructions and data. TDO is tri-stateable and is actively driven in the Shift-IR and Shift-DR controller states. TDO changes on the falling edge of TCK. 11.2.5 Test Reset (TRST) The TRST signal is used to asynchronously initialize the test controller. The TRST signal has an internal pullup resistor. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 11-5 Freescale Semiconductor, Inc. JTAG Port TAP Controller 11.3 TAP CONTROLLER The TAP controller is responsible for interpreting the sequence of logical values on the TMS signal. It is a synchronous state machine that controls the operation of the JTAG logic. The state machine is shown in Figure 11-2. The TAP controller responds to changes at the TMS and TCK signals. Transitions from one state to another occur on the rising edge of TCK. The value shown adjacent to each state transition represents the value of the TMS signal sampled on the rising edge of TCK signal. For a description of the TAP controller states, refer to the IEEE 1149.1 document. Freescale Semiconductor, Inc... Test-Logic-Reset 1 0 Run-Test/Idle 0 1 1 Select-DR-Scan 0 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 0 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 AA0114 1 Select-IR-Scan 0 1 Capture-IR 0 Shift-IR 1 1 0 1 0 Figure 11-2 TAP Controller State Machine 11-6 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. JTAG Port TAP Controller 11.3.1 Boundary Scan Register (BSR) The BSR in the DSP56309 JTAG implementation contains bits for all device signal and clock signals and associated control signals. All DSP56309 bidirectional signals have a single register bit in the BSR for signal data; each such signal is controlled by an associated control bit in the BSR. The DSP56309 BSR bit definitions are described in Table 11-2 on page 11-13. 11.3.2 Instruction Register Freescale Semiconductor, Inc... The DSP56309 JTAG implementation includes the three mandatory public instructions (EXTEST, SAMPLE/PRELOAD, and BYPASS), and also supports the optional CLAMP instruction defined by IEEE 1149.1. The HI-Z public instruction provides the capability for disabling all device output drivers. The ENABLE_ONCE public instruction enables the JTAG port to communicate with the OnCE circuitry. The DEBUG_REQUEST public instruction enables the JTAG port to force the DSP56300 core into debug mode. The DSP56300 core includes a 4-bit instruction register without parity consisting of a shift register with four parallel outputs. Data is transferred from the shift register to the parallel outputs during the Update-IR controller state. Figure 11-3 shows the JTAG instruction register. JTAG Instruction Register (IR) B3 B2 B1 B0 AA0746 Figure 11-3 JTAG Instruction Register The four bits are used to decode the eight unique instructions shown in Table 11-1. All other encodings are reserved for future enhancements and are decoded as BYPASS. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 11-7 Freescale Semiconductor, Inc. JTAG Port TAP Controller Table 11-1 JTAG Instructions Code Instruction B3 0 0 0 B2 0 0 0 0 1 1 1 1 0 1 1 1 B1 0 0 1 1 0 0 1 1 x 0 1 1 B0 0 1 0 1 0 1 0 1 x x 0 1 EXTEST SAMPLE/PRELOAD IDCODE CLAMP HI-Z RESERVED ENABLE_ONCE DEBUG_REQUEST RESERVED RESERVED RESERVED BYPASS Freescale Semiconductor, Inc... 0 0 0 0 0 1 1 1 1 The parallel output of the instruction register is reset to 0010 in the Test-Logic-Reset controller state, which is equivalent to the IDCODE instruction. During the Capture-IR controller state, the parallel inputs to the instruction shift register are loaded with 01 in the LSBs as required by the standard. The two MSBs are loaded with the values of the core status bits OS1 and OS0 from the OnCE controller. See Section 10NOn-Chip Emulation Module for a description of the status bits. 11.3.2.1 EXTEST (B[3:0] = 0000) The external test (EXTEST) instruction selects the BSR. EXTEST also asserts internal reset for the DSP56300 core system logic to force a predictable internal state while performing external boundary scan operations. By using the TAP, the BSR is capable of the following: Scanning user-defined values into the output buffers Capturing values presented to input signals 11-8 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. JTAG Port TAP Controller Controlling the direction of bidirectional signals Controlling the output drive of tri-stateable output signals For more details on the function and use of the EXTEST instruction, please refer to the IEEE 1149.1 document. 11.3.2.2 SAMPLE/PRELOAD (B[3:0] = 0001) The SAMPLE/PRELOAD instruction provides two separate functions. First, it provides a means to obtain a snapshot of system data and control signals. The snapshot occurs on the rising edge of TCK in the Capture-DR controller state. The data can be observed by shifting it transparently through the BSR. Freescale Semiconductor, Inc... Note: Because there is no internal synchronization between the JTAG clock (TCK) and the system clock (CLK), the user must provide some form of external synchronization to achieve meaningful results. The second function of the SAMPLE/PRELOAD instruction is to initialize the BSR output cells prior to selection of EXTEST. This initialization insures that known data appears on the outputs when entering the EXTEST instruction. 11.3.2.3 IDCODE (B[3:0] = 0010) The IDCODE instruction selects the ID register. This instruction is provided as a public instruction to allow the manufacturer, part number, and version of a component to be determined through the TAP. Figure 11-4 shows the ID register configuration. 31 28 27 22 21 17 16 12 11 Manufacturer Identity 10 1 Version Information Design Center Number 0010 Customer Part Number Core Number 00000 Chip Derivative Number 00010 000110 00000001110 1 AA0718 Figure 11-4 JTAG ID Register One application of the ID register is to distinguish the manufacturer(s) of components on a board when multiple sourcing is used. As more components emerge which conform to the IEEE 1149.1 standard, it is desirable to allow for a system diagnostic controller unit to blindly interrogate a board design in order to determine the type of each component in MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 11-9 Freescale Semiconductor, Inc. JTAG Port TAP Controller each location. This information is also available for factory process monitoring and for failure mode analysis of assembled boards. MotorolaOs manufacturer identity is 00000001110. The customer part number consists of two parts: Motorola design center number (bits 27:22) and a sequence number (bits 21:12). The sequence number is divided into two parts: core number (bits 21:17) and chip derivative number (bits 16:12). Motorola Semiconductor Israel (MSIL) design center number is 000110 and DSP56300 core number is 00001. Once the IDCODE instruction is decoded, it selects the ID register, which is a 32-bit data register. Since the Bypass register loads a logical 0 at the start of a scan cycle, whereas the ID register loads a logical 1 into its LSB, examination of the first bit of data shifted out of a component during a test data scan sequence immediately following exit from Test-Logic-Reset controller state shows whether such a register is included in the design. When the IDCODE instruction is selected, the operation of the test logic has no effect on the operation of the on-chip system logic as required by the IEEE 1149.1 standard. 11.3.2.4 CLAMP (B[3:0] = 0011) The CLAMP instruction is not included in the IEEE 1149.1 standard. It is provided as a public instruction that selects the 1-bit bypass register as the serial path between TDI and TDO while allowing signals driven from the component signals to be determined from the BSR. During testing of ICs on PCB, it may be necessary to place static guarding values on signals that control operation of logic not involved in the test. The EXTEST instruction could be used for this purpose, but because it selects the BSR, the required guarding signals would be loaded as part of the complete serial data stream shifted in, both at the start of the test and each time a new test pattern is entered. Since the CLAMP instruction allows guarding values to be applied using the BSR of the appropriate ICs while selecting their bypass registers, it allows much faster testing than does the EXTEST instruction. Data in the boundary scan cell remains unchanged until a new instruction is shifted in or the JTAG state machine is set to its reset state. The CLAMP instruction also asserts internal reset for the DSP56300 core system logic to force a predictable internal state while performing external boundary scan operations. 11.3.2.5 HI-Z (B[3:0] = 0100) The HI-Z instruction is not included in the IEEE 1149.1 standard. It is provided as a manufacturerOs optional public instruction to prevent having to backdrive the output signals during circuit-board testing. When HI-Z is invoked, all output drivers, including the two-state drivers, are turned off (i.e., high impedance). The instruction selects the bypass register. The HI-Z instruction also asserts internal reset for the DSP56300 core system logic to force a predictable internal state while performing external boundary scan operations. Freescale Semiconductor, Inc... 11-10 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. JTAG Port TAP Controller 11.3.2.6 ENABLE_ONCE(B[3:0] = 0110) The ENABLE_ONCE instruction is not included in the IEEE 1149.1 standard. It is provided as a public instruction to allow you to perform system debug functions. When the ENABLE_ONCE instruction is decoded the TDI and TDO signals are connected directly to the OnCE registers. The particular OnCE register connected between TDI and TDO at a given time is selected by the OnCE controller depending on the OnCE instruction being currently executed. All communication with the OnCE controller is done through the Select-DR-Scan path of the JTAG TAP controller. See Section 10NOn-Chip Emulation Module for more information. Freescale Semiconductor, Inc... 11.3.2.7 DEBUG_REQUEST(B[3:0] = 0111) The DEBUG_REQUEST instruction is not included in the IEEE 1149.1 standard. It is provided as a public instruction to allow you to generate a debug request signal to the DSP56300 core. When the DEBUG_REQUEST instruction is decoded, the TDI and TDO signals are connected to the instruction registers. Due to the fact that in the Capture-IR state of the TAP the OnCE status bits are captured in the Instruction shift register, the external JTAG controller must continue to shift-in the DEBUG_REQUEST instruction while polling the status bits that are shifted-out until debug mode is entered (acknowledged by the combination 11 on OS1OS0). After the acknowledgment of debug mode is received, the external JTAG controller must issue the ENABLE_ONCE instruction to allow the user to perform system debug functions. 11.3.2.8 BYPASS (B[3:0] = 1111) The BYPASS instruction selects the single-bit bypass register, as shown in Figure 11-5. This choice creates a shift-register path from TDI to the bypass register, and finally to TDO, circumventing the BSR. This instruction is used to enhance test efficiency when a component other than the DSP56300 core-based device becomes the device under test. When the bypass register is selected by the current instruction, the shift-register stage is set to a logical 0 on the rising edge of TCK in the Capture-DR controller state. Therefore, the first bit shifted out after selecting the bypass register is always a logical 0. Shift DR 0 From TDI G1 1 1 D C CLOCKDR Mux To TDO AA0115 Figure 11-5 Bypass Register MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 11-11 Freescale Semiconductor, Inc. JTAG Port DSP56300 Restrictions 11.4 DSP56300 RESTRICTIONS The control afforded by the output enable signals using the BSR and the EXTEST instruction requires a compatible circuit-board test environment to avoid device-destructive configurations. You must avoid situations in which the DSP56300 core output drivers are enabled into actively driven networks. In addition, the EXTEST instruction can be performed only after power-up or a regular hardware RESET signal while EXTAL was provided. Then during the execution of EXTEST, EXTAL can remain inactive. Freescale Semiconductor, Inc... There are two constraints related to the JTAG interface. First, the TCK input does not include an internal pullup resistor and should not be left unconnected. The second constraint is to insure that the JTAG test logic is kept transparent to the system logic by forcing the TAP into the Test-Logic-Reset controller state, using either of two methods. During power-up, TRST must be externally asserted to force the TAP controller into this state. After power-up is concluded, TMS must be sampled as a logical 1 for five consecutive TCK rising edges. If TMS either remains unconnected or is connected to VCC, then the TAP controller cannot leave the Test-Logic-Reset state, regardless of the state of TCK. The DSP56300 core features a low-power stop mode, which is invoked using the STOP instruction. The interaction of the JTAG interface with low-power Stop mode is as follows: 1. The TAP controller must be in the Test-Logic-Reset state to either enter or remain in the low-power stop mode. Leaving the TAP controller Test-Logic-Reset state negates the ability to achieve low-power, but does not otherwise affect device functionality. 2. The TCK input is not blocked in low-power stop mode. To consume minimal power, the TCK input should be externally connected to VCC or GND. 3. The TMS and TDI signals include on-chip pullup resistors. In low-power stop mode, these two signals should remain either unconnected or connected to VCC to achieve minimal power consumption. Since during stop mode all DSP56309 core clocks are disabled, the JTAG interface provides the means of polling the device status (sampled in the Capture-IR state). 11-12 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. JTAG Port DSP56309 Boundary Scan Register 11.5 DSP56309 BOUNDARY SCAN REGISTER Table 11-2 provides a listing of the contents of the BSR for the DSP56309. Table 11-2 DSP56309 BSR Bit Definitions Bit # 0 1 Cell Type BC_1 BC_1 BC_1 BC_1 BC_6 BC_6 BC_6 BC_6 BC_6 BC_6 BC_6 BC_6 BC_6 BC_1 BC_6 BC_6 BC_6 BC_6 BC_6 BC_6 BC_6 BC_6 Signal Name MODA MODB MODC MODD D23 D22 D21 D20 D19 D18 D17 D16 D15 D[23:12] D14 D13 D12 D11 D10 D9 D8 D7 Signal Type Input Input Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output N Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output BSR Cell Type Data Data Data Data Data Data Data Data Data Data Data Data Data Control Data Data Data Data Data Data Data Data Freescale Semiconductor, Inc... 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 11-13 Freescale Semiconductor, Inc. JTAG Port DSP56309 Boundary Scan Register Table 11-2 DSP56309 BSR Bit Definitions (Continued) Bit # 22 23 24 25 Cell Type BC_6 BC_6 BC_6 BC_6 BC_1 BC_6 BC_6 BC_6 BC_2 BC_2 BC_2 BC_2 BC_2 BC_2 BC_2 BC_2 BC_2 BC_2 BC_2 BC_2 BC_2 BC_2 BC_2 BC_2 Signal Name D6 D5 D4 D3 D[11:0] D2 D1 D0 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Signal Type Input/Output Input/Output Input/Output Input/Output N Input/Output Input/Output Input/Output Output 2 Output 2 Output 2 Output 2 Output 2 Output 2 Output 2 Output 2 Output 2 Output 2 Output 2 Output 2 Output 2 Output 2 Output 2 Output 2 BSR Cell Type Data Data Data Data Control Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Freescale Semiconductor, Inc... 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 11-14 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. JTAG Port DSP56309 Boundary Scan Register Table 11-2 DSP56309 BSR Bit Definitions (Continued) Bit # 46 47 48 49 Cell Type BC_2 BC_2 BC_2 BC_2 BC_2 BC_1 BC_1 BC_1 BC_6 BC_1 BC_6 BC_1 BC_6 BC_1 BC_6 BC_1 BC_6 BC_1 BC_6 BC_1 BC_6 BC_1 BC_6 BC_1 Signal Name MCS RD WR AT CLKOUT EXTAL RESET HAD0 HAD0 HAD1 HAD1 HAD2 HAD2 HAD3 HAD3 HAD4 HAD4 HAD5 HAD5 HAD6 HAD6 HAD7 HAD7 HAS/A0 Signal Type Output Output Output Output Output Input Input N Input/Output N Input/Output N Input/Output N Input/Output N Input/Output N Input/Output N Input/Output N Input/Output N BSR Cell Type Data Data Data Data Data Data Data Control Data Control Data Control Data Control Data Control Data Control Data Control Data Control Data Control Freescale Semiconductor, Inc... 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 11-15 Freescale Semiconductor, Inc. JTAG Port DSP56309 Boundary Scan Register Table 11-2 DSP56309 BSR Bit Definitions (Continued) Bit # 70 71 72 73 Cell Type BC_6 BC_1 BC_6 BC_1 BC_6 BC_1 BC_6 BC_1 BC_6 BC_1 BC_6 BC_1 BC_6 BC_1 BC_6 BC_1 BC_6 BC_1 BC_6 BC_1 BC_6 BC_1 BC_6 BC_1 Signal Name HAS/A0 HA8/A1 HA8/A1 HA9/A2 HA9/A2 HCS/A10 HCS/A10 TIO0 TIO0 TIO1 TIO1 TIO2 TIO2 HREQ/TRQ HREQ/TRQ HACK/RRQ HACK/RRQ HRW/RD HRW/RD HDS/WR HDS/WR SCK0 SCK0 SCK1 Signal Type Input/Output N Input/Output N Input/Output N Input/Output N Input/Output N Input/Output NInput/Output N Input/Output N Input/Output N Input/Output N Input/Output N Input/Output N BSR Cell Type Data Control Data Control Data Control Data Control Data Control Data Control Data Control Data Control Data Control Data Control Data Control Data Control Freescale Semiconductor, Inc... 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 11-16 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. JTAG Port DSP56309 Boundary Scan Register Table 11-2 DSP56309 BSR Bit Definitions (Continued) Bit # 94 95 96 97 Cell Type BC_6 BC_1 BC_6 BC_1 BC_6 BC_1 BC_6 BC_1 BC_6 BC_1 BC_6 BC_1 BC_6 BC_1 BC_6 BC_1 BC_6 BC_1 BC_6 BC_1 BC_6 BC_1 BC_6 BC_1 Signal Name SCK1 GPIO2 GPIO2 GPIO1 GPIO1 GPIO0 GPIO0 SC00 SC00 SC10 SC10 STD0 STD0 SRD0 SRD0 PINIT PINIT DE DE SC01 SC01 SC02 SC02 STD1 Signal Type Input/Output N Input/Output N Input/Output N Input/Output N Input/Output N Input/Output N Input/Output N Input/Output N Input/Output N Input/Output N Input/Output N Input/Output N BSR Cell Type Data Control Data Control Data Control Data Control Data Control Data Control Data Control Data Control Data Control Data Control Data Control Data Control Freescale Semiconductor, Inc... 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D 11-17 Freescale Semiconductor, Inc. JTAG Port DSP56309 Boundary Scan Register Table 11-2 DSP56309 BSR Bit Definitions (Continued) Bit # 118 119 120 121 Cell Type BC_6 BC_1 BC_6 BC_1 BC_6 BC_1 Signal Name STD1 SRD1 SRD1 SC11 SC11 SC12 Signal Type Input/Output N Input/Output N Input/Output N BSR Cell Type Data Control Data Control Data Control Freescale Semiconductor, Inc... 122 123 11-18 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. APPENDIX A BOOTSTRAP PROGRAMS Freescale Semiconductor, Inc... ; BOOTSTRAP CODE FOR DSP56309 - (C) Copyright 1998 Motorola Inc. DSP56302 - (C) Copyright 1995 Motorola Inc. ; Revised March,29 1995. June, 1998. ; ; Bootstrap through the Host Interface, External EPROM or SCI. ; ; This is the Bootstrap program contained in the DSP56309 192-word Boot DSP56302 192-word Boot ; ROM. This program can load any program RAM segment from an external ; EPROM, from the Host Interface or from the SCI serial interface. ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ; If MD:MC:MB:MA=1000, then the Boot ROM is bypassed and the DSP56309 will DSP56302 will ; start fetching instructions beginning with the address $8000 assuming that ; an external memory of SRAM type is used. The accesses will be performed ; using 31 wait states with no address attributes selected (default area). MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D A-1 Freescale Semiconductor, Inc. Bootstrap Programs ; BOOTSTRAP CODE FOR DSP56309 - (C) Copyright 1997 Motorola Inc. ; Revised March, 18 1997. ; ; Bootstrap through the Host Interface, External EPROM or SCI. ; ; This is the Bootstrap program contained in the DSP56309 192-word Boot ; ROM. This program can load any program RAM segment from an external ; EPROM, from the Host Interface or from the SCI serial interface. ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; If MD:MC:MB:MA=x000, then the Boot ROM is bypassed and the DSP56309 ; will start fetching instructions beginning with address $C00000 (MD=0) ; or $008000 (MD=1) assuming that an external memory of SRAM type is ; used. The accesses will be performed using 31 wait states with no ; address attributes selected (default area). ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Operation modes MD:MC:MB:MA=0001-0111 are reserved. ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; If MD:MC:MB:MA=1001, then it loads a program RAM segment from consecutive ; byte-wide P memory locations, starting at P:$D00000 (bits 7-0). ; The memory is selected by the Address Attribute AA1 and is accessed with ; 31 wait states. ; The EPROM bootstrap code expects to read 3 bytes ; specifying the number of program words, 3 bytes specifying the address ; to start loading the program words and then 3 bytes for each program ; word to be loaded. The number of words, the starting address and the ; program words are read least significant byte first followed by the ; mid and then by the most significant byte. ; The program words will be condensed into 24-bit words and stored in ; contiguous PRAM memory locations starting at the specified starting address. ; After reading the program words, program execution starts from the same ; address where loading started. ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; If MD:MC:MB:MA=1010, then it loads the program RAM from the SCI interface. ; The number of program words to be loaded and the starting address must ; be specified. The SCI bootstrap code expects to receive 3 bytes ; specifying the number of program words, 3 bytes specifying the address ; to start loading the program words and then 3 bytes for each program ; word to be loaded. The number of words, the starting address and the ; program words are received least significant byte first followed by the ; mid and then by the most significant byte. After receiving the ; program words, program execution starts in the same address where ; loading started. The SCI is programmed to work in asynchronous mode ; with 8 data bits, 1 stop bit and no parity. The clock source is ; external and the clock frequency must be 16x the baud rate. ; After each byte is received, it is echoed back through the SCI Freescale Semiconductor, Inc... A-2 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Bootstrap Programs ; transmitter. ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Operation mode MD:MC:MB:MA=1011 is reserved. ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; If MD:MC:MB:MA=1100, then it loads the program RAM from the Host ; Interface programmed to operate in the ISA mode. ; The HOST ISA bootstrap code expects to read a 24-bit word ; specifying the number of program words, a 24-bit word specifying the address ; to start loading the program words and then a 24-bit word for each program ; word to be loaded. The program words will be stored in ; contiguous PRAM memory locations starting at the specified starting address. ; After reading the program words, program execution starts from the same ; address where loading started. ; The Host Interface bootstrap load program may be stopped by ; setting the Host Flag 0 (HF0). This will start execution of the loaded ; program from the specified starting address. ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; If MD:MC:MB:MA=1101, then it loads the program RAM from the Host ; Interface programmed to operate in the HC11 non multiplexed mode. ; ; The HOST HC11 bootstrap code expects to read a 24-bit word ; specifying the number of program words, a 24-bit word specifying the address ; to start loading the program words and then a 24-bit word for each program ; word to be loaded. The program words will be stored in ; contiguous PRAM memory locations starting at the specified starting address. ; After reading the program words, program execution starts from the same ; address where loading started. ; The Host Interface bootstrap load program may be stopped by ; setting the Host Flag 0 (HF0). This will start execution of the loaded ; program from the specified starting address. ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; If MD:MC:MB:MA=1110, then it loads the program RAM from the Host ; Interface programmed to operate in the 8051 multiplexed bus mode, ; in double-strob pin configuration. ; The HOST 8051 bootstrap code expects accesses that are byte wide. ; The HOST 8051 bootstrap code expects to read 3 bytes forming a 24-bit word ; specifying the number of program words, 3 bytes forming a 24-bit word ; specifying the address to start loading the program words and then 3 bytes ; forming 24-bit words for each program word to be loaded. ; The program words will be stored in contiguous PRAM memory locations ; starting at the specified starting address. ; After reading the program words, program execution starts from the same ; address where loading started. ; The Host Interface bootstrap load program may be stopped by setting the ; Host Flag 0 (HF0). This will start execution of the loaded program from Freescale Semiconductor, Inc... MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D A-3 Freescale Semiconductor, Inc. Bootstrap Programs Freescale Semiconductor, Inc... ; the specified starting address. ; ; The base address of the HI08 in multiplexed mode is 0x80 and is not ; modified by the bootstrap code. All the address lines are enabled ; and should be connected accordingly. ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; If MD:MC:MB:MA=1111, then it loads the program RAM from the Host ; Interface programmed to operate in the MC68302 (IMP) bus mode, ; in single-strob pin configuration. ; The HOST MC68302 bootstrap code expects accesses that are byte wide. ; The HOST MC68302 bootstrap code expects to read 3 bytes forming a 24-bit word ; specifying the number of program words, 3 bytes forming a 24-bit word ; specifying the address to start loading the program words and then 3 bytes ; forming 24-bit words for each program word to be loaded. ; The program words will be stored in contiguous PRAM memory locations ; starting at the specified starting address. ; After reading the program words, program execution starts from the same ; address where loading started. ; The Host Interface bootstrap load program may be stopped by setting the ; Host Flag 0 (HF0). This will start execution of the loaded program from ; the specified starting address. ; ;;;;;;;;;;;;;;;;;;;; MEMORY EQUATES ;;;;;;;;;;;;;;;;;;;;;;;; page 132,55,0,0,0 opt mex EQUALDATA equ 1 ;; 1 if xram and yram are of equal ;; size and addresses, 0 otherwise. if start_dram length_dram else start_xram length_xram start_yram length_yram endif start_pram length_pram (EQUALDATA) equ 0 equ $1c00 equ equ equ equ 0 $1c00 0 $1c00 ;; 24k X and Y RAM ;; same addresses ;; 7k XRAM ;; 7k YRAM equ equ 0 $5000 ;; 20k PRAM ;; ;;;;;;;;;;;;;;;;;;;; GENERAL EQUATES ;;;;;;;;;;;;;;;;;;;;;;;; ;; BOOT equ $D00000 ; ; ; ; this is the location in P memory on the external memory bus where the external byte-wide EPROM would be located A-4 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Bootstrap Programs AARV equ $D00409 ; AAR1 selects the EPROM as CE~ ; mapped as P from $D00000 to ; $DFFFFF, active low ;; ;;;;;;;;;;;;;;;;;;;; DSP I/O REGISTERS ;;;;;;;;;;;;;;;;;;;;;;;; ;; M_PDRC M_PRRC M_SSR M_STXL M_SRXL M_SCCR M_SCR M_PCRE M_AAR1 M_HPCR M_HSR M_HRX HRDF HF0 HEN SCK0 EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU $FFFFBD $FFFFBE $FFFF93 $FFFF95 $FFFF98 $FFFF9B $FFFF9C $FFFF9F $FFFFF8 $FFFFC4 $FFFFC3 $FFFFC6 $0 $3 $6 $3 ;; Port C GPIO Data Register ;; Port C Direction Register ; SCI Status Register ; SCI Transmit Data Register (low) ; SCI Receive Data Register (low) ; SCI Clock Control Register ; SCI Control Register ; Port E Control register ; Address Attribute Register 1 ; Host Polarity Control Register ; Host Status Rgister ; Host Recceive Register ; Host Receive Data Full ; Host Flag 0 ; Host Enable ;; SCK0 is bit #3 as GPIO Freescale Semiconductor, Inc... ORG PL:$ff0000,PL:$ff0000 START clr a jclr #3,omr,OMR0XXX jclr #2,omr,EPRSCILD jclr #1,omr,OMR1IS0 jclr #0,omr,I8051HOSTLD ; ; ; ; ; ; ; bootstrap code starts at $ff0000 clear a If MD:MC:MB:MA=0xxx, If MD:MC:MB:MA=10xx, IF MD:MC:MB:MA=110x, If MD:MC:MB:MA=1110, If MD:MC:MB:MA=1111, go to OMR0XXX load from EPROM/SCI look for ISA/HC11 load from 8051 Host load from MC68302 Host ;======================================================================== ; This is the routine which loads a program through the HI08 host port ; The program is downloaded from the host MCU with the following rules: ; 1) 3 bytes - Define the program length. ; 2) 3 bytes - Define the address to which to start loading the program to. ; 3) 3n bytes (while n is any integer number) ; The program words will be stroed in contiguous PRAM memory locations starting ; at the specified starting address. ; After reading the program words, program execution starts from the same ; address where loading started. ; The host MCU may terminate the loading process by setting the HF1=0 and HF0=1. ; When the downloading is terminated, the program will start execution of the ; loaded program from the specified starting address. ; The HI08 boot ROM program enables the following busses to download programs ; through the HI08 port: ; MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D A-5 Freescale Semiconductor, Inc. Bootstrap Programs ; 1 - ISA - Dual strobes non-multiplexed bus with negative strobe ; pulses duale positive request ; 2 - HC11 - Single strobe non-multiplexed bus with positive strobe ; pulse single negative request. ; 4 - i8051 - Dual strobes multiplexed bus with negative strobe pulses ; dual negative request. ; 5 - MC68302 - Single strobe non-multiplexed bus with negative strobe ; pulse single negative request. ;======================================================================== MC68302HOSTLD movep Freescale Semiconductor, Inc... bra OMR1IS0 #%0000000000111000,x:M_HPCR ; Configure ; HAP = 0 ; HRP = 0 ; HCSP = 0 ; HD/HS = 0 ; HMUX = 0 ; HASP = 0 ; ; HDSP = 0 ; HROD = 0 ; spare = 0 ; ; HEN = 0 ; ; HAEN = 1 ; HREN = 1 ; HCSEN = 1 ; HA9EN = 0 ; ; HA8EN = 0 ; ; HGEN = 0 jset #0,omr,HC11HOSTLD ; If MD:MC:MB:MA=1101, go load from HC11 Host ; If MD:MC:MB:MA=1100, go load from ISA HOST ISAHOSTLD movep #%0101000000011000,x:M_HPCR ; Configure ; HAP = 0 ; HRP = 1 ; HCSP = 0 ; HD/HS = 1 ; HMUX = 0 ; HASP = 0 ; ; HDSP = 0 ; HROD = 0 ; spare = 0 ; the following conditions: Negative host acknowledge Positive host request Negatice chip select input Dual strobes bus (RD and WR) Non multiplexed bus (address strobe polarity has no meaning in non-multiplexed bus) Negative data stobes polarity Host request is active when enabled This bit should be set to 0 for future compatability A-6 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Bootstrap Programs ; ; ; ; ; ; ; ; ; ; bra HC11HOSTLD movep = 0 When the HPCR register is modified HEN should be cleared = 0 Host acknowledge is disabled = 1 Host requests are enabled = 1 Host chip select input enabled = 0 (address 9 enable bit has no meaning in non-multiplexed bus) = 0 (address 8 enable bit has no meaning non-multiplexed bus) = 0 Host GPIO pins are disabled Freescale Semiconductor, Inc... bra I8051HOSTLD movep #%0000001000011000,x:M_HPCR ; Configure ; HAP = 0 ; HRP = 0 ; HCSP = 0 ; HD/HS = 0 ; HMUX = 0 ; HASP = 0 ; ; HDSP = 1 ; HROD = 0 ; spare = 0 ; ; HEN = 0 ; ; HAEN = 0 ; HREN = 1 ; HCSEN = 1 ; HA9EN = 0 ; ; HA8EN = 0 ; ; HGEN = 0 the following conditions: Negative host acknowledge Negatice host request Negatice chip select input Dual strobes bus (RD and WR) Multiplexed bus Positive address strobe polarity Negative data stobes polarity Host request is active when enabled This bit should be set to 0 for future compatability When the HPCR register is modified HEN should be cleared Host acknowledge is disabled Host requests are enabled MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D A-7 Freescale Semiconductor, Inc. Bootstrap Programs ; ; ; ; HI08CONT bset jclr movep jclr HCSEN HA9EN HA8EN HGEN = = = = 1 1 1 0 Host chip select input enabled Enable address 9 input Enable address 8 input Host GPIO pins are disabled #HEN,x:M_HPCR #HRDF,x:M_HSR,* x:M_HRX,a0 #HRDF,x:M_HSR,* x:M_HRX,r0 r0,r1 a0,HI08LOOP #HRDF,x:M_HSR,HI08NW #HF0,x:M_HSR,HI08LL ; ; ; ; Enable the HI08 to operate as host interface (set HEN=1) wait for the program length to be written ; wait for the program starting address ; to be written Freescale Semiconductor, Inc... movep move do HI08LL jset jclr enddo bra HI08NW movep ; set a loop with the downloaded length ; ; ; ; ; If new word was loaded then jump to read that word If HF0=0 then continue with the downloading Must terminate the do loop ; starting address for load A-8 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Bootstrap Programs move a1,r1 do a0,_LOOP7 do #3,_LOOP8 jclr #2,X:M_SSR,* movep X:M_SRXL,A2 jclr #1,X:M_SSR,* movep a2,X:M_STXL asr #8,a,a _LOOP8 movem a1,p:(r0)+ nop _LOOP7 ; save starting address ; Receive program words ; ; ; ; Wait for RDRF to go high Put 8 bits in A2 Wait for TDRE to go high echo the received byte ; Store 24-bit result in P mem. ; pipeline delay ; Boot from SCI done Freescale Semiconductor, Inc... bra do #6,_LOOP9 movem p:(r2)+,a2 asr #8,a,a _LOOP9 move a1,r0 move a1,r1 ; ; ; ; ; ; ; read number of words and starting address Get the 8 LSB from ext. P mem. Shift 8 bit data into A1 starting address for load save it in r1 a0 holds the number of words ; read program words ; Each instruction has 3 bytes ; Get the 8 LSB from ext. P mem. ; Shift 8 bit data into A1 _LOOP11 ; Go get another byte. movem a1,p:(r0)+ ; Store 24-bit result in P mem. nop ; pipeline delay _LOOP10 ; and go get another 24-bit word. ; Boot from EPROM done ;======================================================================== FINISH ; This is the exit handler that returns execution to normal ; expanded mode and jumps to the RESET vector. andi #$0,ccr jmp (r1) ; Clear CCR as if RESET to 0. ; Then go to starting Prog addr. do a0,_LOOP10 do #3,_LOOP11 movem p:(r2)+,a2 asr #8,a,a ;======================================================================== ; The following modes are reserved, some of which are used for internal testing MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D A-9 Freescale Semiconductor, Inc. Bootstrap Programs ; Can be implemented in future. ; OMR0XXX jclr #2,omr,EPRSCILD ; If MD:MC:MB:MA=00xx, jclr #1,omr,OMR1IS0 ; IF MD:MC:MB:MA=010x, jclr #0,omr,I8051HOSTLD ; If MD:MC:MB:MA=0110, ; If MD:MC:MB:MA=0111, default default default execute to EPROM/SCI to ISA/HC11 to 8051 Host burnin test ;======================================================================== ; This mode is reserved for internal testing purposes ; MD:MC:MB:MA=0111 ;;--------------------------------------------------------;; ;; burnin mode ;; ;; Intended to be used for burn-in test. Wake up from reset ;; with PINIT set for execution in maximum frequency. ;; All RAM locations are validated, arithmetic/logic operations ;; are validated (add, eor) and exercised (mac). ;; While all tests pass, the SCK0 pin will continue to toggle. ;; When the test fails the DSP enters DEBUG and stops execution. ;; ;;--------------------------------------------------------;; get PATTERN pointer clr b #PATTERNS,r6 move #<(NUM_PATTERNS-1),m6 Freescale Semiconductor, Inc... ;; b is the error accumulator ;; program runs forever in ;; cyclic form ;; configure SCK0 as gpio output. PRRC register is cleared at reset. movep b,x:M_PDRC ;; clear GPIO data register bset #SCK0,x:M_PRRC ;; Define SCK0 as output GPIO pin ;; SCK0 toggles means test pass do #9,burn1 ;;---------------------------;; test RAM ;; each pass checks 1 pattern ;;---------------------------move p:(r6)+,x1 ;; pattern for x memory move p:(r6)+,x0 ;; pattern for y memory move p:(r6)+,y0 ;; pattern for p memory ;; write pattern to all memory locations if (EQUALDATA) ;; write x and y memory clr a #start_dram,r0 move #>length_dram,n0 rep n0 mac x0,x1,a x,l:(r0)+ ;; x/y ram symmetrical ;; start of x/y ram ;; length of x/y ram ;; exercise mac, write x/y ram A-10 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Bootstrap Programs else ;; write x memory clr a #start_xram,r0 move #>length_xram,n0 rep n0 mac x0,y0,a x1,x:(r0)+ ;; write y memory clr a #start_yram,r1 move #>length_yram,n1 rep n1 mac x1,y0,a x0,y:(r1)+ ;; x/y ram not symmetrical ;; start of xram ;; length of xram ;; exercise mac, write xram ;; start of yram ;; length of yram ;; exercise mac, write yram Freescale Semiconductor, Inc... endif ;; write p memory clr a #start_pram,r2 move #>length_pram,n2 rep n2 move y0,p:(r2)+ ;; check memory contents if (EQUALDATA) ;; check dram clr a #start_dram,r0 do n0,_loopd move x:(r0),a1 eor x1,a add a,b move y:(r0)+,a1 eor x0,a add a,b _loopd else ;; check xram clr a #start_xram,r0 do n0,_loopx move x:(r0)+,a1 eor x1,a add a,b _loopx ;; check yram clr a #start_yram,r1 do n1,_loopy move y:(r1)+,a1 eor x0,a add a,b ;; x/y ram not symmetrical ;; x/y ram symmetrical ;; start of pram ;; length of pram ;; write pram ;; restore pointer, clear a ;; a0=a2=0 ;; accumulate error in b ;; a0=a2=0 ;; accumulate error in b ;; restore pointer, clear a ;; a0=a2=0 ;; accumulate error in b ;; restore pointer, clear a ;; a0=a2=0 ;; accumulate error in b MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D A-11 Freescale Semiconductor, Inc. Bootstrap Programs _loopy endif ;; check pram clr a #start_pram,r2 do n2,_loopp move p:(r2)+,a1 eor y0,a add a,b _loopp ;;--------------------------------------------------;; toggle pin if no errors, stop execution otherwise. ;;--------------------------------------------------beq label1 bclr #SCK0,x:M_PDRC ;; clear sck0 if error, enddo ;; terminate the loop normally bra Freescale Semiconductor, Inc... label1 burn1 wait ;; enter wait after test completion PATTERNS ORG PL:,PL: dsm 4 ;; align for correct modulo addressing ORG PL:PATTERNS,PL:PATTERNS ;; Each value is written to all memories dc dc dc dc $555555 $AAAAAA $333333 $F0F0F0 *-PATTERNS NUM_PATTERNS equ end A-12 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. APPENDIX B EQUATES Freescale Semiconductor, Inc... ;***************************************************************************** ; ; EQUATES for DSP56309 I/O registers and ports 56302 I/O registers and ports ; ; Last update: March11 1995 June 1998 ; ;***************************************************************************** page opt ioequ ident 1,0 132,55,0,0,0 mex ;------------------------------------------------------------------------ MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D B-1 Freescale Semiconductor, Inc. Equates B.1 B.2 B.3 B.4 B.5 B.6 B.7 B.8 B.9 B.10 Freescale Semiconductor, Inc... I/O EQUATES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3 HOST INTERFACE (HI08) EQUATES . . . . . . . . . . . . . . . . . B-3 SCI EQUATES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4 ESSI EQUATES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5 EXCEPTION PROCESSING EQUATES. . . . . . . . . . . . . . . . B-7 TIMER MODULE EQUATES . . . . . . . . . . . . . . . . . . . . . . . . . B-9 DIRECT MEMORY ACCESS (DMA) EQUATES. . . . . . . . . B-10 PHASE-LOCKED LOOP (PLL) EQUATES . . . . . . . . . . . . . B-12 BUS INTERFACE UNIT (BIU) EQUATES . . . . . . . . . . . . . . B-13 INTERRUPT EQUATES . . . . . . . . . . . . . . . . . . . . . . . . . . . B-15 B-2 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Equates B.1 I/O EQUATES ;-----------------------------------------------------------------------; ;I/O Port Programming ; ;-----------------------------------------------------------------------; Register Addresses M_HDR M_HDDR M_PCRC M_PRRC M_PDRC M_PCRD M_PRRD M_PDRD M_PCRE M_PRRE M_PDRE M_OGDB EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU $FFFFC9 $FFFFC8 $FFFFBF $FFFFBE $FFFFBD $FFFFAF $FFFFAE $FFFFAD $FFFF9F $FFFF9E $FFFF9D $FFFFFC ; ; ; ; ; ; ; ; ; ; ; ; Host Host Port Port Port Port Port Port Port Port Port OnCE port GPIO data Register port GPIO direction Register C Control Register C Direction Register C GPIO Data Register D Control register D Direction Data Register D GPIO Data Register E Control register E Direction Register E Data Register GDB Register Freescale Semiconductor, Inc... B.2 HOST INTERFACE (HI08) EQUATES ;-----------------------------------------------------------------------Host Interface (HI08) Equates ;-----------------------------------------------------------------------; Register Addresses M_HCR M_HSR M_HPCR M_HBAR M_HRX M_HTX ; M_HRIE M_HTIE M_HCIE M_HF2 M_HF3 ; M_HRDF M_HTDE M_HCP EQU EQU EQU EQU EQU EQU $FFFFC2 $FFFFC3 $FFFFC4 $FFFFC5 $FFFFC6 $FFFFC7 ; ; ; ; ; ; Host Host Host Host Host Host Control Register Status Register Polarity Control Register Base Address Register Receive Register Transmit Register HCR bits definition EQU EQU EQU EQU EQU $0 $1 $2 $3 $4 ; ; ; ; ; Host Host Host Host Host Receive interrupts Enable Transmit Interrupt Enable Command Interrupt Enable Flag 2 Flag 3 HSR bits definition EQU EQU EQU $0 $1 $2 ; Host Receive Data Full ; Host Receive Data Empty ; Host Command Pending MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D B-3 Freescale Semiconductor, Inc. Equates M_HF0 M_HF1 ; M_HGEN M_HA8EN M_HA9EN M_HCSEN M_HREN M_HAEN M_HEN M_HOD M_HDSP M_HASP M_HMUX M_HD_HS M_HCSP M_HRP M_HAP EQU EQU $3 $4 ; Host Flag 0 ; Host Flag 1 HPCR bits definition EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU $0 $1 $2 $3 $4 $5 $6 $8 $9 $A $B $C $D $E $F ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Host Host Host Host Host Host Host Host Host Host Host Host Host Host Host Port GPIO Enable Address 8 Enable Address 9 Enable Chip Select Enable Request Enable Acknowledge Enable Enable Request Open Drain mode Data Strobe Polarity Address Strobe Polarity Multiplexed bus select Double/Single Strobe select Chip Select Polarity Request Polarity Acknowledge Polarity Freescale Semiconductor, Inc... B.3 SCI EQUATES ;-----------------------------------------------------------------------;Serial Communications Interface (SCI) Equates ;-----------------------------------------------------------------------; Register Addresses M_STXH M_STXM M_STXL M_SRXH M_SRXM M_SRXL M_STXA M_SCR M_SSR M_SCCR ; M_WDS M_WDS0 M_WDS1 M_WDS2 M_SSFTD M_SBK M_WAKE EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU $FFFF97 $FFFF96 $FFFF95 $FFFF9A $FFFF99 $FFFF98 $FFFF94 $FFFF9C $FFFF93 $FFFF9B ; ; ; ; ; ; ; ; ; ; SCI SCI SCI SCI SCI SCI SCI SCI SCI SCI Transmit Data Register (high) Transmit Data Register (middle) Transmit Data Register (low) Receive Data Register (high) Receive Data Register (middle) Receive Data Register (low) Transmit Address Register Control Register Status Register Clock Control Register SCI Control Register Bit Flags EQU EQU EQU EQU EQU EQU EQU $7 0 1 2 3 4 5 ; ; ; ; ; ; ; Word Select Mask (WDS0-WDS3) Word Select 0 Word Select 1 Word Select 2 SCI Shift Direction Send Break Wakeup Mode Select B-4 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Equates M_RWU M_WOMS M_SCRE M_SCTE M_ILIE M_SCRIE M_SCTIE M_TMIE M_TIR M_SCKP M_REIE ; EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 6 7 8 9 10 11 12 13 14 15 16 ; ; ; ; ; ; ; ; ; ; ; Receiver Wakeup Enable Wired-OR Mode Select SCI Receiver Enable SCI Transmitter Enable Idle Line Interrupt Enable SCI Receive Interrupt Enable SCI Transmit Interrupt Enable Timer Interrupt Enable Timer Interrupt Rate SCI Clock Polarity SCI Error Interrupt Enable (REIE) SCI Status Register Bit Flags EQU EQU EQU EQU EQU EQU EQU EQU 0 1 2 3 4 5 6 7 ; ; ; ; ; ; ; ; Transmitter Empty Transmit Data Register Empty Receive Data Register Full Idle Line Flag Overrun Error Flag Parity Error Framing Error Flag Received Bit 8 (R8) Address Freescale Semiconductor, Inc... M_TRNE M_TDRE M_RDRF M_IDLE M_OR M_PE M_FE M_R8 ; M_CD M_COD M_SCP M_RCM M_TCM SCI Clock Control Register EQU EQU EQU EQU EQU $FFF 12 13 14 15 ; ; ; ; ; Clock Divider Mask (CD0-CD11) Clock Out Divider Clock Prescaler Receive Clock Mode Source Bit Transmit Clock Source Bit B.4 ESSI EQUATES ;-----------------------------------------------------------------------;Enhanced Synchronous Serial Interface (ESSI) Equates ;-----------------------------------------------------------------------; Register Addresses Of SSI0 M_TX00 M_TX01 M_TX02 M_TSR0 M_RX0 M_SSISR0 M_CRB0 M_CRA0 M_TSMA0 M_TSMB0 EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU $FFFFBC $FFFFBB $FFFFBA $FFFFB9 $FFFFB8 $FFFFB7 $FFFFB6 $FFFFB5 $FFFFB4 $FFFFB3 ; ; ; ; ; ; ; ; ; ; SSI0 SSIO SSIO SSI0 SSI0 SSI0 SSI0 SSI0 SSI0 SSI0 Transmit Data Register 0 Transmit Data Register 1 Transmit Data Register 2 Time Slot Register Receive Data Register Status Register Control Register B Control Register A Transmit Slot Mask Register A Transmit Slot Mask Register B MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D B-5 Freescale Semiconductor, Inc. Equates M_RSMA0 EQU M_RSMB0 EQU ; $FFFFB2 $FFFFB1 ; SSI0 Receive Slot Mask Register A ; SSI0 Receive Slot Mask Register B Register Addresses Of SSI1 EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU $FFFFAC $FFFFAB $FFFFAA $FFFFA9 $FFFFA8 $FFFFA7 $FFFFA6 $FFFFA5 $FFFFA4 $FFFFA3 $FFFFA2 $FFFFA1 ; ; ; ; ; ; ; ; ; ; ; ; SSI1 SSI1 SSI1 SSI1 SSI1 SSI1 SSI1 SSI1 SSI1 SSI1 SSI1 SSI1 Transmit Data Register 0 Transmit Data Register 1 Transmit Data Register 2 Time Slot Register Receive Data Register Status Register Control Register B Control Register A Transmit Slot Mask Register A Transmit Slot Mask Register B Receive Slot Mask Register A Receive Slot Mask Register B Freescale Semiconductor, Inc... M_TX10 M_TX11 M_TX12 M_TSR1 M_RX1 M_SSISR1 M_CRB1 M_CRA1 M_TSMA1 M_TSMB1 M_RSMA1 M_RSMB1 ; M_PM M_PSR M_DC M_ALC M_WL M_SSC1 ; M_OF M_OF0 M_OF1 M_SCD M_SCD0 M_SCD1 M_SCD2 M_SCKD M_SHFD M_FSL M_FSL0 M_FSL1 M_FSR M_FSP M_CKP M_SYN M_MOD M_SSTE M_SSTE2 M_SSTE1 M_SSTE0 M_SSRE M_SSTIE M_SSRIE SSI Control Register A Bit Flags EQU EQU EQU EQU EQU EQU $FF 11 $1F000 18 $380000 22 ; ; ; ; ; ; Prescale Modulus Select Mask (PM0-PM7) Prescaler Range Frame Rate Divider Control Mask (DC0-DC7) Alignment Control (ALC) Word Length Control Mask (WL0-WL7) Select SC1 as TR #0 drive enable (SSC1) SSI Control Register B Bit Flags EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU $3 0 1 $1C 2 3 4 5 6 $180 7 8 9 10 11 12 13 $1C000 14 15 16 17 18 19 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Serial Output Flag Mask Serial Output Flag 0 Serial Output Flag 1 Serial Control Direction Mask Serial Control 0 Direction Serial Control 1 Direction Serial Control 2 Direction Clock Source Direction Shift Direction Frame Sync Length Mask (FSL0-FSL1) Frame Sync Length 0 Frame Sync Length 1 Frame Sync Relative Timing Frame Sync Polarity Clock Polarity Sync/Async Control SSI Mode Select SSI Transmit enable Mask SSI Transmit #2 Enable SSI Transmit #1 Enable SSI Transmit #0 Enable SSI Receive Enable SSI Transmit Interrupt Enable SSI Receive Interrupt Enable B-6 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Equates M_STLIE M_SRLIE M_STEIE M_SREIE ; M_IF M_IF0 M_IF1 M_TFS M_RFS M_TUE M_ROE M_TDE M_RDF ; EQU EQU EQU EQU 20 21 22 23 ; ; ; ; SSI SSI SSI SSI Transmit Last Slot Interrupt Enable Receive Last Slot Interrupt Enable Transmit Error Interrupt Enable Receive Error Interrupt Enable SSI Status Register Bit Flags EQU EQU EQU EQU EQU EQU EQU EQU EQU $3 0 1 2 3 4 5 6 7 ; ; ; ; ; ; ; ; ; Serial Input Flag Mask Serial Input Flag 0 Serial Input Flag 1 Transmit Frame Sync Flag Receive Frame Sync Flag Transmitter Underrun Error FLag Receiver Overrun Error Flag Transmit Data Register Empty Receive Data Register Full Freescale Semiconductor, Inc... SSI Transmit Slot Mask Register A $FFFF ; SSI Transmit Slot Bits Mask A (TS0-TS15) M_SSTSA EQU ; SSI Transmit Slot Mask Register B $FFFF ; SSI Transmit Slot Bits Mask B (TS16-TS31) M_SSTSB EQU ; SSI Receive Slot Mask Register A $FFFF ; SSI Receive Slot Bits Mask A (RS0-RS15) M_SSRSA EQU ; SSI Receive Slot Mask Register B $FFFF ; SSI Receive Slot Bits Mask B (RS16-RS31) M_SSRSB EQU B.5 EXCEPTION PROCESSING EQUATES ;-----------------------------------------------------------------------Exception Processing Equates ;-----------------------------------------------------------------------; Register Addresses M_IPRC M_IPRP ; M_IAL M_IAL0 M_IAL1 M_IAL2 M_IBL EQU EQU $FFFFFF $FFFFFE ; Interrupt Priority Register Core ; Interrupt Priority Register Peripheral Interrupt Priority Register Core (IPRC) EQU EQU EQU EQU EQU $7 0 1 2 $38 ; ; ; ; ; IRQA IRQA IRQA IRQA IRQB Mode Mode Mode Mode Mode Mask Interrupt Priority Level (low) Interrupt Priority Level (high) Trigger Mode Mask MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D B-7 Freescale Semiconductor, Inc. Equates Freescale Semiconductor, Inc... M_IBL0 M_IBL1 M_IBL2 M_ICL M_ICL0 M_ICL1 M_ICL2 M_IDL M_IDL0 ;(low) M_IDL1 ;(high) M_IDL2 M_D0L M_D0L0 M_D0L1 M_D1L M_D1L0 M_D1L1 M_D2L M_D2L0 M_D2L1 M_D3L M_D3L0 M_D3L1 M_D4L M_D4L0 M_D4L1 M_D5L M_D5L0 M_D5L1 ; M_HPL M_HPL0 M_HPL1 M_S0L M_S0L0 M_S0L1 M_S1L M_S1L0 M_S1L1 M_SCL M_SCL0 M_SCL1 M_T0L M_T0L0 M_T0L1 EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 3 4 5 $1C0 6 7 8 $E00 9 10 11 $3000 12 13 $C000 14 15 $30000 16 17 $C0000 18 19 $300000 20 21 $C00000 22 23 ; ; ; ; ; ; ; ; ; IRQB IRQB IRQB IRQC IRQC IRQC IRQC IRQD IRQD Mode Mode Mode Mode Mode Mode Mode Mode Mode Interrupt Priority Interrupt Priority Trigger Mode Mask Interrupt Priority Interrupt Priority Trigger Mode Mask Interrupt Priority Level (low) Level (high) Level (low) Level (high) Level ; IRQD Mode Interrupt Priority Level ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; IRQD DMA0 DMA0 DMA0 DMA1 DMA1 DMA1 DMA2 DMA2 DMA2 DMA3 DMA3 DMA3 DMA4 DMA4 DMA4 DMA5 DMA5 DMA5 Mode Trigger Mode Interrupt priority Interrupt Priority Interrupt Priority Interrupt Priority Interrupt Priority Interrupt Priority Interrupt priority Interrupt Priority Interrupt Priority Interrupt Priority Interrupt Priority Interrupt Priority Interrupt priority Interrupt Priority Interrupt Priority Interrupt priority Interrupt Priority Interrupt Priority Level Level Level Level Level Level Level Level Level Level Level Level Level Level Level Level Level Level Mask (low) (high) Mask (low) (high) Mask (low) (high) Mask (low) (high) Mask (low) (high) Mask (low) (high) Interrupt Priority Register Peripheral (IPRP) EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU $3 0 1 $C 2 3 $30 4 5 $C0 6 7 $300 8 9 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Host Interrupt Priority Level Mask Host Interrupt Priority Level (low) Host Interrupt Priority Level (high) SSI0 Interrupt Priority Level Mask SSI0 Interrupt Priority Level (low) SSI0 Interrupt Priority Level (high) SSI1 Interrupt Priority Level Mask SSI1 Interrupt Priority Level (low) SSI1 Interrupt Priority Level (high) SCI Interrupt Priority Level Mask SCI Interrupt Priority Level (low) SCI Interrupt Priority Level (high) TIMER Interrupt Priority Level Mask TIMER Interrupt Priority Level (low) TIMER Interrupt Priority Level (high) B-8 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Equates B.6 TIMER MODULE EQUATES ;--------------------------------------------------------------;Timer Module Equates ;--------------------------------------------------------------; Register Addresses Of TIMER0 M_TCSR0 M_TLR0 M_TCPR0 M_TCR0 ; M_TCSR1 M_TLR1 M_TCPR1 M_TCR1 ; M_TCSR2 M_TLR2 M_TCPR2 M_TCR2 M_TPLR M_TPCR ; M_TE M_TOIE M_TCIE M_TC M_INV M_TRM M_DIR M_DI M_DO M_PCE M_TOF M_TCF ; M_PS M_PS0 M_PS1 ; EQU EQU EQU EQU $FFFF8F $FFFF8E $FFFF8D $FFFF8C ; ; ; ; TIMER0 TIMER0 TIMER0 TIMER0 Control/Status Register Load Register Compare Register Count Register Freescale Semiconductor, Inc... Register Addresses Of TIMER1 EQU EQU EQU EQU $FFFF8B $FFFF8A $FFFF89 $FFFF88 ; ; ; ; TIMER1 TIMER1 TIMER1 TIMER1 Control/Status Register Load Register Compare Register Count Register Register Addresses Of TIMER2 EQU EQU EQU EQU EQU EQU $FFFF87 $FFFF86 $FFFF85 $FFFF84 $FFFF83 $FFFF82 ; ; ; ; ; ; TIMER2 Control/Status Register TIMER2 Load Register TIMER2 Compare Register TIMER2 Count Register TIMER Prescaler Load Register TIMER Prescaler Count Register Timer Control/Status Register Bit Flags EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 0 1 2 $F0 8 9 11 12 13 15 20 21 ; ; ; ; ; ; ; ; ; ; ; ; Timer Enable Timer Overflow Interrupt Enable Timer Compare Interrupt Enable Timer Control Mask TC(3:0) Inverter Bit Timer Restart Mode Direction Bit Data Input Data Output Prescaled Clock Enable Timer Overflow Flag Timer Compare Flag Timer Prescaler Register Bit Flags EQU EQU EQU $600000 21 22 ; Prescaler Source Mask Timer Control Bits MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D B-9 Freescale Semiconductor, Inc. Equates M_TC0 M_TC1 M_TC2 M_TC3 EQU EQU EQU EQU 4 5 6 7 ; ; ; ; Timer Timer Timer Timer Control Control Control Control 0 1 2 3 B.7 DIRECT MEMORY ACCESS (DMA) EQUATES ;------------------------------------------------------------------------ Freescale Semiconductor, Inc... ;Direct Memory Access (DMA) Equates ;-----------------------------------------------------------------------; Register Addresses Of DMA M_DSTR M_DOR0 M_DOR1 M_DOR2 M_DOR3 ; M_DSR0 M_DDR0 M_DCO0 M_DCR0 ; M_DSR1 M_DDR1 M_DCO1 M_DCR1 ; M_DSR2 M_DDR2 M_DCO2 M_DCR2 ; M_DSR3 M_DDR3 M_DCO3 M_DCR3 ; EQU EQU EQU EQU EQU $FFFFF4 $FFFFF3 $FFFFF2 $FFFFF1 $FFFFF0 ; ; ; ; ; DMA DMA DMA DMA DMA Status Offset Offset Offset Offset Register Register Register Register Register 0 1 2 3 Register Addresses Of DMA0 EQU EQU EQU EQU $FFFFEF $FFFFEE $FFFFED $FFFFEC ; ; ; ; DMA0 DMA0 DMA0 DMA0 Source Address Register Destination Address Register Counter Control Register Register Addresses Of DMA1 EQU EQU EQU EQU $FFFFEB $FFFFEA $FFFFE9 $FFFFE8 ; ; ; ; DMA1 DMA1 DMA1 DMA1 Source Address Register Destination Address Register Counter Control Register Register Addresses Of DMA2 EQU EQU EQU EQU $FFFFE7 $FFFFE6 $FFFFE5 $FFFFE4 ; ; ; ; DMA2 DMA2 DMA2 DMA2 Source Address Register Destination Address Register Counter Control Register Register Addresses Of DMA4 EQU EQU EQU EQU $FFFFE3 $FFFFE2 $FFFFE1 $FFFFE0 ; ; ; ; DMA3 DMA3 DMA3 DMA3 Source Address Register Destination Address Register Counter Control Register Register Addresses Of DMA4 B-10 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Equates M_DSR4 M_DDR4 M_DCO4 M_DCR4 ; M_DSR5 M_DDR5 M_DCO5 M_DCR5 EQU EQU EQU EQU $FFFFDF $FFFFDE $FFFFDD $FFFFDC ; ; ; ; DMA4 DMA4 DMA4 DMA4 Source Address Register Destination Address Register Counter Control Register Register Addresses Of DMA5 EQU EQU EQU EQU $FFFFDB $FFFFDA $FFFFD9 $FFFFD8 ; ; ; ; DMA5 DMA5 DMA5 DMA5 Source Address Register Destination Address Register Counter Control Register Freescale Semiconductor, Inc... ; M_DSS DMA Control Register EQU $3 ; DMA Source Space Mask ;(DSS0-Dss1) M_DSS0 M_DSS1 M_DDS EQU EQU EQU 0 1 $C ; DMA Source Memory space 0 ; DMA Source Memory space 1 ; DMA Destination Space Mask ;(DDS-DDS1) M_DDS0 M_DDS1 M_DAM EQU EQU EQU 2 3 $3f0 ; DMA Destination Memory Space 0 ; DMA Destination Memory Space 1 ; DMA Address Mode Mask ;(DAM5-DAM0) M_DAM0 M_DAM1 M_DAM2 M_DAM3 M_DAM4 M_DAM5 M_D3D M_DRS M_DCON M_DPR M_DPR0 M_DPR1 M_DTM EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 4 5 6 7 8 9 10 $F800 16 $60000 17 18 $380000 ; ; ; ; ; ; ; ; ; ; ; ; ; DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA Address Mode 0 Address Mode 1 Address Mode 2 Address Mode 3 Address Mode 4 Address Mode 5 Three Dimensional Mode Request Source Mask (DRS0-DRS4) Continuous Mode Channel Priority Channel Priority Level (low) Channel Priority Level (high) Transfer Mode Mask ;(DTM2-DTM0) M_DTM0 M_DTM1 M_DTM2 M_DIE M_DE EQU EQU EQU EQU EQU 19 20 21 22 23 ; ; ; ; ; DMA DMA DMA DMA DMA Transfer Mode 0 Transfer Mode 1 Transfer Mode 2 Interrupt Enable bit Channel Enable bit MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D B-11 Freescale Semiconductor, Inc. Equates ; M_DTD M_DTD0 M_DTD1 M_DTD2 M_DTD3 M_DTD4 M_DTD5 M_DACT M_DCH DMA Status Register EQU EQU EQU EQU EQU EQU EQU EQU EQU $3F 0 1 2 3 4 5 8 $E00 ;Channel Transfer Done Status MASK ; DMA Channel Transfer Done Status ; DMA Channel Transfer Done Status ; DMA Channel Transfer Done Status ; DMA Channel Transfer Done Status ; DMA Channel Transfer Done Status ; DMA Channel Transfer Done Status ; DMA Active State ; DMA Active Channel Mask 0 1 2 3 4 5 Freescale Semiconductor, Inc... ;(DCH0DCH2) M_DCH0 M_DCH1 M_DCH2 EQU EQU EQU 9 10 11 ; DMA Active Channel 0 ; DMA Active Channel 1 ; DMA Active Channel 2 B.8 PHASE-LOCKED LOOP (PLL) EQUATES ;--------------------------------------------------------------;Phase Locked Loop (PLL) equates ;--------------------------------------------------------------; Register Addresses Of PLL M_PCTL ; M_MF M_DF M_XTLR M_XTLD M_PSTP M_PEN M_PCOD M_PD EQU $FFFFFD ; PLL Control Register PLL Control Register EQU EQU EQU EQU EQU EQU EQU EQU $FFF $7000 15 16 17 18 19 $F00000 ; ; ; ; ; ; ; ; Multiplication Factor Bit Mask (MF0-MF11) Division Factor Bit Mask (DF0-DF2) XTAL Range select bit XTAL Disable Bit STOP Processing State Bit PLL Enable Bit PLL Clock Output Disable Bit PreDivider Factor Bit Mask (PD0-PD3) B-12 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Equates B.9 BUS INTERFACE UNIT (BIU) EQUATES ;--------------------------------------------------------------;Bus Interface Unit (BIU) Equates ;--------------------------------------------------------------; Register Addresses Of BIU M_BCR M_DCR M_AAR0 M_AAR1 M_AAR2 M_AAR3 M_IDR ; M_BA0W M_BA1W M_BA2W M_BA3W M_BDFW M_BBS M_BLH M_BRH ; M_BCW M_BRW M_BPS M_BPLE M_BME M_BRE M_BSTR M_BRF M_BRP ; M_BAT ; M_BAAP M_BPEN M_BXEN M_BYEN M_BAM M_BPAC EQU EQU EQU EQU EQU EQU EQU $FFFFFB $FFFFFA $FFFFF9 $FFFFF8 $FFFFF7 $FFFFF6 $FFFFF5 ; ; ; ; ; ; ; Bus Control Register DRAM Control Register Address Attribute Register Address Attribute Register Address Attribute Register Address Attribute Register ID Register Freescale Semiconductor, Inc... 0 1 2 3 Bus Control Register EQU EQU EQU EQU EQU EQU EQU EQU $1F $3E0 $1C00 $E000 $1F0000 21 22 23 ; ; ; ; ; ; ; ; Area 0 Wait Control Mask (BA0W0-BA0W4) Area 1 Wait Control Mask (BA1W0-BA14) Area 2 Wait Control Mask (BA2W0-BA2W2) Area 3 Wait Control Mask (BA3W0-BA3W3) Default Area Wait Control Mask (BDFW0-BDFW4) Bus State Bus Lock Hold Bus Request Hold DRAM Control Register EQU EQU EQU EQU EQU EQU EQU EQU EQU $3 $C $300 11 12 13 14 $7F8000 23 ; ; ; ; ; ; ; ; ; In Page Wait States Bit Mask (BCW0-BCW1) Out Of Page Wait States Bit Mask (BRW0-BRW1) DRAM Page Size Bit Mask (BPS0-BPS1) Page Logic Enable Mastership Enable Refresh Enable Software Triggered Refresh Refresh Rate Bits Mask (BRF0-BRF7) Refresh prescaler Address Attribute Registers EQU $3 ; External Access Type and Pin Definition Bits Mask BAT(1:0) EQU EQU EQU EQU EQU EQU 2 3 4 5 6 7 ; ; ; ; ; ; Address Attribute Pin Polarity Program Space Enable X Data Space Enable Y Data Space Enable Address Muxing Packing Enable MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D B-13 Freescale Semiconductor, Inc. Equates M_BNC M_BAC ; M_CP M_CA M_V M_Z M_N M_U M_E M_L M_S M_I0 M_I1 M_S0 M_S1 M_SC M_DM M_LF M_FV M_SA M_CE M_SM M_RM M_CP0 M_CP1 ; M_CDP M_MA M_MB M_MC M_MD M_EBD M_SD M_MS M_CDP0 M_CDP1 M_BEN M_TAS M_BRT M_ATE M_XYS M_EUN M_EOV M_WRP M_SEN EQU EQU $F00 $FFF000 ; Number of Address Bits to Compare Mask ; Address to Compare Bits Mask BAC(11:0) control and status bits in SR EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU $c00000 0 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 19 20 21 22 23 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; mask for CORE-DMA priority bits in SR Carry Overflow Zero Negative Unnormalized Extension Limit Scaling Bit Interrupt Mask Bit 0 Interrupt Mask Bit 1 Scaling Mode Bit 0 Scaling Mode Bit 1 Sixteen_Bit Compatibility Double Precision Multiply DO-Loop Flag DO-Forever Flag Sixteen-Bit Arithmetic Instruction Cache Enable Arithmetic Saturation Rounding Mode bit 0 of priority bits in SR bit 1 of priority bits in SR Freescale Semiconductor, Inc... control and status bits in OMR EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU $300 0 1 2 3 4 6 7 8 9 10 11 12 15 16 17 18 19 20 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; mask for CORE-DMA priority bits in OMR Operating Mode A Operating Mode B Operating Mode C Operating Mode D External Bus Disable bit in OMR Stop Delay Memory Switch bit in OMR bit 0 of priority bits in OMR bit 1 of priority bits in OMR Burst Enable TA Synchronize Select Bus Release Timing Address Tracing Enable bit in OMR. Stack Extension space select bit in OMR. Extended stack UNderflow flag in OMR. Extended stack OVerflow flag in OMR. Extended WRaP flag in OMR. Stack Extension Enable bit in OMR. B-14 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Equates B.10 INTERRUPT EQUATES ;*************************************************************** ; EQUATES for DSP56309 interrupts ;************************************************************** ;--------------------------------------------------------------; Non-Maskable interrupts Freescale Semiconductor, Inc... ;--------------------------------------------------------------I_RESET EQU I_VEC+$00 ; Hardware RESET I_STACK EQU I_VEC+$02 ; Stack Error I_ILL EQU I_VEC+$04 ; Illegal Instruction I_DBG EQU I_VEC+$06 ; Debug Request I_TRAP EQU I_VEC+$08 ; Trap I_NMI EQU I_VEC+$0A ; Non Maskable Interrupt ;--------------------------------------------------------------; Interrupt Request Pins ;--------------------------------------------------------------I_IRQA EQU I_VEC+$10 ; IRQA I_IRQB EQU I_VEC+$12 ; IRQB I_IRQC EQU I_VEC+$14 ; IRQC I_IRQD EQU I_VEC+$16 ; IRQD ;--------------------------------------------------------------; DMA Interrupts ;--------------------------------------------------------------I_DMA0 EQU I_VEC+$18 ; DMA Channel 0 I_DMA1 EQU I_VEC+$1A ; DMA Channel 1 I_DMA2 EQU I_VEC+$1C ; DMA Channel 2 I_DMA3 EQU I_VEC+$1E ; DMA Channel 3 I_DMA4 EQU I_VEC+$20 ; DMA Channel 4 I_DMA5 EQU I_VEC+$22 ; DMA Channel 5 ;--------------------------------------------------------------; Timer Interrupts ;--------------------------------------------------------------I_TIM0C EQU I_VEC+$24 ; TIMER 0 compare I_TIM0OF EQU I_VEC+$26 ; TIMER 0 overflow I_TIM1C EQU I_VEC+$28 ; TIMER 1 compare I_TIM1OF EQU I_VEC+$2A ; TIMER 1 overflow I_TIM2C EQU I_VEC+$2C ; TIMER 2 compare I_TIM2OF EQU I_VEC+$2E ; TIMER 2 overflow ;--------------------------------------------------------------- MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D B-15 Freescale Semiconductor, Inc. Equates ; ESSI Interrupts ;--------------------------------------------------------------I_SI0RD EQU I_VEC+$30 ; ESSI0 Receive Data I_SI0RDE EQU I_VEC+$32 ; ESSI0 Receive Data With Exception Status I_SI0RLS EQU I_VEC+$34 ; ESSI0 Receive last slot I_SI0TD EQU I_VEC+$36 ; ESSI0 Transmit data I_SI0TDE EQU I_VEC+$38 ; ESSI0 Transmit Data With Exception Status I_SI0TLS EQU I_VEC+$3A ; ESSI0 Transmit last slot I_SI1RD EQU I_VEC+$40 ; ESSI1 Receive Data I_SI1RDE EQU I_VEC+$42 ; ESSI1 Receive Data With Exception Status I_SI1RLS EQU I_VEC+$44 ; ESSI1 Receive last slot I_SI1TD EQU I_VEC+$46 ; ESSI1 Transmit data I_SI1TDE EQU I_VEC+$48 ; ESSI1 Transmit Data With Exception Status I_SI1TLS EQU I_VEC+$4A ; ESSI1 Transmit last slot ;--------------------------------------------------------------; SCI Interrupts ;--------------------------------------------------------------I_SCIRD EQU I_VEC+$50 ; SCI Receive Data I_SCIRDE EQU I_VEC+$52 ; SCI Receive Data With Exception Status I_SCITD EQU I_VEC+$54 ; SCI Transmit Data I_SCIIL EQU I_VEC+$56 ; SCI Idle Line I_SCITM EQU I_VEC+$58 ; SCI Timer ;--------------------------------------------------------------; HOST Interrupts ;--------------------------------------------------------------I_HRDF EQU I_VEC+$60 ; Host Receive Data Full I_HTDE EQU I_VEC+$62 ; Host Transmit Data Empty I_HC EQU I_VEC+$64 ; Default Host Command ;--------------------------------------------------------------; INTERRUPT ENDING ADDRESS ;--------------------------------------------------------------I_INTEND EQU I_VEC+$FF ; last address of interrupt vector space Freescale Semiconductor, Inc... B-16 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. APPENDIX C DSP56309 BSDL LISTING Freescale Semiconductor, Inc... ------ MOTOROLA SSDT JTAG SOFTWARE BSDL File Generated: Mon Apr 8 10:13:47 1996 Revision History: entity DSP56309 is DSP56303 is generic (PHYSICAL_PIN_MAP : string := "TQFP144"); port ( DE_:inout SC02:inout SC01:inout SC00:inout STD0:inout SCK0:inout bit; bit; bit; bit; bit; bit; MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D C-1 Freescale Semiconductor, Inc. DSP56309 BSDL Listing -- M O T O R O L A S S D T J T A G S O F T W A R E -- BSDL File Generated: Tue Mar 3 15:14:41 1998 --- Revision History: -entity DSP56309 is generic (PHYSICAL_PIN_MAP : string := OTQFP144O); port ( DE_N:inout SC02:inout SC01:inout SC00:inout STD0:inout SCK0:inout SRD0:inout SRD1:inout SCK1:inout STD1:inout SC10:inout SC11:inout SC12:inout TXD:inout SCLK:inout RXD:inout TIO0:inout TIO1:inout TIO2:inout HAD:inout HREQ:inout MODD:in MODC:in MODB:in MODA:in D:inout A:out EXTAL:in XTAL:linkage RD_N:out WR_N:out AA:out BR_N:buffer BG_N:in BB_N:inout PCAP:linkage RESET_N:in PINIT:in TA_N:in CAS_N:out BCLK:out BCLK_N:out CLKOUT:buffer TRST_N:in bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit_vector(0 bit; bit; bit; bit; bit; bit_vector(0 bit_vector(0 bit; bit; bit; bit; bit_vector(0 bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; Freescale Semiconductor, Inc... to 7); to 23); to 17); to 3); C-2 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. DSP56309 BSDL Listing Freescale Semiconductor, Inc... TDO:out TDI:in TCK:in TMS:in RESERVED:linkage SGND:linkage SVCC:linkage QGND:linkage QVCC:linkage HGND:linkage HVCC:linkage DGND:linkage DVCC:linkage AGND:linkage AVCC:linkage JVCC:linkage JGND1:linkage JGND:linkage HACK:inout HDS:inout HRW:inout CVCC:linkage CGND:linkage HCS:inout HA9:inout HA8:inout HAS:inout bit; bit; bit; bit; bit_vector(0 bit_vector(0 bit_vector(0 bit_vector(0 bit_vector(0 bit; bit; bit_vector(0 bit_vector(0 bit_vector(0 bit_vector(0 bit; bit; bit; bit; bit; bit; bit_vector(0 bit_vector(0 bit; bit; bit; bit); to to to to to 1); 1); 1); 3); 3); to to to to 3); 3); 3); 3); to 1); to 1); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of DSP56309 : entity is OSTD_1149_1_1993O; attribute PIN_MAP of DSP56309 : entity is PHYSICAL_PIN_MAP; constant TQFP144 : PIN_MAP_STRING := OSRD1: 1, O & OSTD1: 2, O & OSC02: 3, O & OSC01: 4, O & ODE_N: 5, O & OPINIT: 6, O & OSRD0: 7, O & OSVCC: (8, 25), O & OSGND: (9, 26), O & OSTD0: 10, O & OSC10: 11, O & OSC00: 12, O & ORXD: 13, O & OTXD: 14, O & OSCLK: 15, O & OSCK1: 16, O & OSCK0: 17, O & OQVCC: (18, 56, 91, 126), O & MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D C-3 Freescale Semiconductor, Inc. DSP56309 BSDL Listing Freescale Semiconductor, Inc... OQGND: ORESERVED: OHDS: OHRW: OHACK: OHREQ: OTIO2: OTIO1: OTIO0: OHCS: OHA9: OHA8: OHAS: OHAD: OHVCC: OHGND: ORESET_N: OJVCC: OPCAP: OJGND: OJGND1: OAA: OCAS_N: OXTAL: OEXTAL: OCVCC: OCGND: OCLKOUT: OBCLK: OBCLK_N: OTA_N: OBR_N: OBB_N: OWR_N: ORD_N: OBG_N: OA: OAVCC: OAGND: OD: ODVCC: ODGND: OMODD: OMODC: OMODB: OMODA: OTRST_N: OTDO: OTDI: OTCK: OTMS: OSC12: (19, 54, 90, 127), O & (49, 20), O & 21, O & 22, O & 23, O & 24, O & 27, O & 28, O & 29, O & 30, O & 31, O & 32, O & 33, O & (43, 42, 41, 40, 37, 36, 35, 34), O & 38, O & 39, O & 44, O & 45, O & 46, O & 47, O & 48, O & (70, 69, 51, 50), O & 52, O & 53, O & 55, O & (57, 65), O & (58, 66), O & 59, O & 60, O & 61, O & 62, O & 63, O & 64, O & 67, O & 68, O & 71, O & (72, 73, 76, 77, 78, 79, 82, 83, 84, 85, 88, 89, 92, 93, 94, 97, 98, 99), O & (74, 80, 86, 95), O & (75, 81, 87, 96), O & (100, 101, 102, 105, 106, 107, 108, 109, 110, 113, 114, 115, 116, 117, O & O 118, 121, 122, 123, 124, 125, 128, 131, 132, 133), O & (103, 111, 119, 129), O & (104, 112, 120, 130), O & 134, O & 135, O & 136, O & 137, O & 138, O & 139, O & 140, O & 141, O & 142, O & 143, O & C-4 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. DSP56309 BSDL Listing OSC11: attribute attribute attribute attribute attribute 144 O; TAP_SCAN_IN TAP_SCAN_OUT TAP_SCAN_MODE TAP_SCAN_RESET TAP_SCAN_CLOCK of TDI : of TDO : of TMS : of TRST_N : of TCK : signal signal signal signal signal is is is is is true; true; true; true; (20.0e6, BOTH); attribute INSTRUCTION_LENGTH of DSP56309 : entity is 4; attribute INSTRUCTION_OPCODE of DSP56309 : entity is OEXTEST (0000),O & OSAMPLE (0001),O & OIDCODE (0010),O & OCLAMP (0101),O & OHIGHZ (0100),O & OENABLE_ONCE (0110),O & ODEBUG_REQUEST(0111),O & OBYPASS (1111)O; attribute INSTRUCTION_CAPTURE of DSP56309 : entity is O0001O; attribute IDCODE_REGISTER of DSP56309 : entity is O0010O & -- version O000110O & -- manufacturerOs use O0000000010O & -- sequence number O00000001110O & -- manufacturer identity O1O; -- 1149.1 requirement Freescale Semiconductor, Inc... attribute REGISTER_ACCESS of DSP56309 : entity is OONCE[8] (ENABLE_ONCE,DEBUG_REQUEST)O ; attribute BOUNDARY_LENGTH of DSP56309 : entity is 144; attribute -- num O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 BOUNDARY_REGISTER of DSP56309 : entity is cell port func safe [ccell dis (BC_1, MODA, input, X),O & (BC_1, MODB, input, X),O & (BC_1, MODC, input, X),O & (BC_1, MODD, input, X),O & (BC_6, D(23), bidir, X, 13, (BC_6, D(22), bidir, X, 13, (BC_6, D(21), bidir, X, 13, (BC_6, D(20), bidir, X, 13, (BC_6, D(19), bidir, X, 13, (BC_6, D(18), bidir, X, 13, (BC_6, D(17), bidir, X, 13, (BC_6, D(16), bidir, X, 13, (BC_6, D(15), bidir, X, 13, (BC_1, *, control, 1),O & (BC_6, D(14), bidir, X, 13, (BC_6, D(13), bidir, X, 13, (BC_6, D(12), bidir, X, 13, rslt] 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, Z),O Z),O Z),O Z),O Z),O Z),O Z),O Z),O Z),O & & & & & & & & & Z),O & Z),O & Z),O & MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D C-5 Freescale Semiconductor, Inc. DSP56309 BSDL Listing O17 O18 O19 -- num O20 O21 O22 O23 O24 O25 O26 O27 O28 O29 O30 O31 O32 O33 O34 O35 O36 O37 O38 O39 -- num O40 O41 O42 O43 O44 O45 O46 O47 O48 O49 O50 O51 O52 O53 O54 O55 O56 O57 O58 O59 -- num O60 O61 O62 O63 O64 O65 O66 (BC_6, (BC_6, (BC_6, cell (BC_6, (BC_6, (BC_6, (BC_6, (BC_6, (BC_6, (BC_1, (BC_6, (BC_6, (BC_6, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, cell (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_6, (BC_1, cell (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, D(11), bidir, D(10), bidir, D(9), bidir, port func D(8), bidir, D(7), bidir, D(6), bidir, D(5), bidir, D(4), bidir, D(3), bidir, *, control, D(2), bidir, D(1), bidir, D(0), bidir, A(17), output3, A(16), output3, A(15), output3, *, control, A(14), output3, A(13), output3, A(12), output3, A(11), output3, A(10), output3, A(9), output3, port func A(8), output3, A(7), output3, A(6), output3, *, control, A(5), output3, A(4), output3, A(3), output3, A(2), output3, A(1), output3, A(0), output3, BG_N, input, AA(0), output3, AA(1), output3, RD_N, output3, WR_N, output3, *, control, *, control, *, control, BB_N, bidir, BR_N, output2, port func TA_N, input, BCLK_N, output3, BCLK, output3, CLKOUT, output2, *, control, *, control, *, control, X, 26, X, 26, X, 26, safe [ccell dis X, 26, X, 26, X, 26, X, 26, X, 26, X, 26, 1),O & X, 26, X, 26, X, 26, X, 33, X, 33, X, 33, 1),O & X, 33, X, 33, X, 33, X, 33, X, 33, X, 33, safe [ccell dis X, 43, X, 43, X, 43, 1),O & X, 43, X, 43, X, 43, X, 43, X, 43, X, 43, X),O & X, 55, X, 56, X, 64, X, 64, 1),O & 1),O & 1),O & X, 57, X),O & safe [ccell dis X),O & X, 64, X, 64, X),O & 1),O & 1),O & 1),O & 1, Z),O 1, Z),O 1, Z),O rslt] 1, Z),O 1, Z),O 1, Z),O 1, Z),O 1, Z),O 1, Z),O 1, 1, 1, 1, 1, 1, Z),O Z),O Z),O Z),O Z),O Z),O & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & Freescale Semiconductor, Inc... 1, Z),O 1, Z),O 1, Z),O 1, Z),O 1, Z),O 1, Z),O rslt] 1, Z),O 1, Z),O 1, Z),O 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, Z),O Z),O Z),O Z),O Z),O Z),O Z),O Z),O Z),O Z),O 1, Z),O & rslt] 1, 1, Z),O & Z),O & C-6 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. DSP56309 BSDL Listing O67 O68 O69 O70 O71 O72 O73 O74 O75 O76 O77 O78 O79 -- num O80 O81 O82 O83 O84 O85 O86 O87 O88 O89 O90 O91 O92 O93 O94 O95 O96 O97 O98 O99 -- num O100 O101 O102 O103 O104 O105 O106 O107 O108 O109 O110 O111 O112 O113 O114 O115 O116 O117 (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, cell (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, cell (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, *, control, EXTAL, input, CAS_N, output3, AA(2), output3, AA(3), output3, RESET_N, input, *, control, HAD(0), bidir, *, control, HAD(1), bidir, *, control, HAD(2), bidir, *, control, port func HAD(3), bidir, *, control, HAD(4), bidir, *, control, HAD(5), bidir, *, control, HAD(6), bidir, *, control, HAD(7), bidir, *, control, HAS, bidir, *, control, HA8, bidir, *, control, HA9, bidir, *, control, HCS, bidir, *, control, TIO0, bidir, *, control, port func TIO1, bidir, *, control, TIO2, bidir, *, control, HREQ, bidir, *, control, HACK, bidir, *, control, HRW, bidir, *, control, HDS, bidir, *, control, SCK0, bidir, *, control, SCK1, bidir, *, control, SCLK, bidir, *, control, 1),O & X),O & X, 65, X, 66, X, 67, X),O & 1),O & X, 73, 1),O & X, 75, 1),O & X, 77, 1),O & safe [ccell dis X, 79, 1),O & X, 81, 1),O & X, 83, 1),O & X, 85, 1),O & X, 87, 1),O & X, 89, 1),O & X, 91, 1),O & X, 93, 1),O & X, 95, 1),O & X, 97, 1),O & safe [ccell dis X, 99, 1),O & X, 101, 1),O & X, 103, 1),O & X, 105, 1),O & X, 107, 1),O & X, 109, 1),O & X, 111, 1),O & X, 113, 1),O & X, 115, 1),O & 1, 1, 1, Z),O & Z),O & Z),O & 1, 1, 1, Z),O & Z),O & Z),O & Freescale Semiconductor, Inc... rslt] 1, Z),O & 1, 1, 1, 1, 1, 1, 1, 1, 1, Z),O & Z),O & Z),O & Z),O & Z),O & Z),O & Z),O & Z),O & Z),O & rslt] 1, Z),O & 1, 1, 1, 1, 1, 1, 1, 1, Z),O & Z),O & Z),O & Z),O & Z),O & Z),O & Z),O & Z),O & MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D C-7 Freescale Semiconductor, Inc. DSP56309 BSDL Listing Freescale Semiconductor, Inc... O118 O119 -- num O120 O121 O122 O123 O124 O125 O126 O127 O128 O129 O130 O131 O132 O133 O134 O135 O136 O137 O138 O139 -- num O140 O141 O142 O143 end DSP56309 TQFP; (BC_6, (BC_1, cell (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, cell (BC_1, (BC_6, (BC_1, (BC_6, TXD, bidir, *, control, port func RXD, bidir, *, control, SC00, bidir, *, control, SC10, bidir, *, control, STD0, bidir, *, control, SRD0, bidir, PINIT, input, *, control, DE_N, bidir, *, control, SC01, bidir, *, control, SC02, bidir, *, control, STD1, bidir, *, control, SRD1, bidir, port func *, control, SC11, bidir, *, control, SC12, bidir, X, 117, 1),O & safe [ccell dis X, 119, 1),O & X, 121, 1),O & X, 123, 1),O & X, 125, 1),O & X, 127, X),O & 1),O & X, 130, 1),O & X, 132, 1),O & X, 134, 1),O & X, 136, 1),O & X, 138, safe [ccell dis 1),O & X, 140, 1),O & X, 142, 1, Z),O & rslt] 1, Z),O & 1, 1, 1, 1, Z),O & Z),O & Z),O & Z),O & 1, 1, 1, 1, Z),O & Z),O & Z),O & Z),O & 1, Z),O & rslt] 1, 1, Z),O & Z)O; ---------------------------------------------------------------------- M O T O R O L A S S D T J T A G S O F T W A R E -- BSDL File Generated: Wed May 20 10:37:28 1998 --- Revision History: --- 1) Date : Tue Mar 3 15:14:41 1998 -Changes : Created for DSP56309 rev0, PBGA --- 2) Date : Wed May 20 10:37:28 1998 -Changes : Fix in definition of DE_N, it is Pull1 when disabled -Updated by Roman Sajman -entity DSP56309 is generic (PHYSICAL_PIN_MAP : string := OTQFP144O); port ( DE_N: SC02: SC01: SC00: inout inout inout inout bit; bit; bit; bit; C-8 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. DSP56309 BSDL Listing STD0: SCK0: SRD0: SRD1: SCK1: STD1: SC10: SC11: SC12: TXD: SCLK: RXD: TIO0: TIO1: TIO2: HAD: HREQ: MODD: MODC: MODB: MODA: D: A: EXTAL: XTAL: RD_N: WR_N: AA: BR_N: BG_N: BB_N: PCAP: RESET_N: PINIT: TA_N: CAS_N: BCLK: BCLK_N: CLKOUT: TRST_N: TDO: TDI: TCK: TMS: RESERVED: SGND: SVCC: QGND: QVCC: HGND: HVCC: DGND: DVCC: inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout in in in in inout out in linkage out out out buffer in inout linkage in in in out out out buffer in out in in in linkage linkage linkage linkage linkage linkage linkage linkage linkage bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit_vector(0 bit; bit; bit; bit; bit; bit_vector(0 bit_vector(0 bit; bit; bit; bit; bit_vector(0 bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit_vector(0 bit_vector(0 bit_vector(0 bit_vector(0 bit_vector(0 bit; bit; bit_vector(0 bit_vector(0 Freescale Semiconductor, Inc... to 7); to 23); to 17); to 3); to to to to to 1); 1); 1); 3); 3); to 3); to 3); MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D C-9 Freescale Semiconductor, Inc. DSP56309 BSDL Listing Freescale Semiconductor, Inc... AGND: AVCC: JVCC: JGND1: JGND: HACK: HDS: HRW: CVCC: CGND: HCS: HA9: HA8: HAS: linkage linkage linkage linkage linkage inout inout inout linkage linkage inout inout inout inout bit_vector(0 bit_vector(0 bit; bit; bit; bit; bit; bit; bit_vector(0 bit_vector(0 bit; bit; bit; bit); to 3); to 3); to 1); to 1); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of DSP56309 : entity is OSTD_1149_1_1993O; attribute PIN_MAP of DSP56309 : entity is PHYSICAL_PIN_MAP; constant TQFP144 : OSRD1: OSTD1: OSC02: OSC01: ODE_N: OPINIT: OSRD0: OSVCC: OSGND: OSTD0: OSC10: OSC00: ORXD: OTXD: OSCLK: OSCK1: OSCK0: OQVCC: OQGND: ORESERVED: OHDS: OHRW: OHACK: OHREQ: OTIO2: OTIO1: OTIO0: OHCS: OHA9: OHA8: OHAS: PIN_MAP_STRING := 1, O & 2, O & 3, O & 4, O & 5, O & 6, O & 7, O & (8, 25), O & (9, 26), O & 10, O & 11, O & 12, O & 13, O & 14, O & 15, O & 16, O & 17, O & (18, 56, 91, 126), O & (19, 54, 90, 127), O & (49, 20), O & 21, O & 22, O & 23, O & 24, O & 27, O & 28, O & 29, O & 30, O & 31, O & 32, O & 33, O & C-10 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. DSP56309 BSDL Listing Freescale Semiconductor, Inc... OHAD: OHVCC: OHGND: ORESET_N: OJVCC: OPCAP: OJGND: OJGND1: OAA: OCAS_N: OXTAL: OEXTAL: OCVCC: OCGND: OCLKOUT: OBCLK: OBCLK_N: OTA_N: OBR_N: OBB_N: OWR_N: ORD_N: OBG_N: OA: 99), O & OAVCC: OAGND: OD: 118, 121, O & (43, 38, 39, 44, 45, 46, 47, 48, (70, 52, 53, 55, (57, (58, 59, 60, 61, 62, 63, 64, 67, 68, 71, (72, 42, 41, 40, 37, 36, 35, 34), O & O& O& O& O& O& O& O& 69, 51, 50), O & O& O& O& 65), O & 66), O & O& O& O& O& O& O& O& O& O& 73, 76, 77, 78, 79, 82, 83, 84, 85, 88, 89, 92, 93, 94, 97, 98, (74, 80, 86, 95), O & (75, 81, 87, 96), O & (100, 101, 102, 105, 106, 107, 108, 109, 110, 113, 114, 115, 116, 117, O122, 123, 124, 125, 128, 131, 132, 133), O & ODVCC: (103, 111, 119, 129), O & ODGND: (104, 112, 120, 130), O & OMODD: 134, O & OMODC: 135, O & OMODB: 136, O & OMODA: 137, O & OTRST_N: 138, O & OTDO: 139, O & OTDI: 140, O & OTCK: 141, O & OTMS: 142, O & OSC12: 143, O & OSC11: 144 O; attribute attribute attribute attribute attribute TAP_SCAN_IN TAP_SCAN_OUT TAP_SCAN_MODE TAP_SCAN_RESET TAP_SCAN_CLOCK of TDI : of TDO : of TMS : of TRST_N : of TCK : signal signal signal signal signal is is is is is true; true; true; true; (20.0e6, BOTH); attribute INSTRUCTION_LENGTH of DSP56309 : entity is 4; attribute INSTRUCTION_OPCODE of DSP56309 : entity is MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D C-11 Freescale Semiconductor, Inc. DSP56309 BSDL Listing OEXTEST OSAMPLE OIDCODE OCLAMP OHIGHZ OENABLE_ONCE ODEBUG_REQUEST OBYPASS (0000),O (0001),O (0010),O (0101),O (0100),O (0110),O (0111),O (1111)O; & & & & & & & Freescale Semiconductor, Inc... attribute INSTRUCTION_CAPTURE of DSP56309 : entity is O0001O; attribute IDCODE_REGISTER of DSP56309 : entity is O0010O & -- version O000110O & -- manufacturerOs use O0000000010O & -- sequence number O00000001110O & -- manufacturer identity O1O; -- 1149.1 requirement attribute REGISTER_ACCESS of DSP56309 : entity is OONCE[8] (ENABLE_ONCE,DEBUG_REQUEST)O ; attribute BOUNDARY_LENGTH of DSP56309 : entity is 144; attribute -- num O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O19 -- num O20 O21 O22 O23 O24 O25 O26 O27 BOUNDARY_REGISTER of DSP56309 : entity is cell port func safe [ccell dis (BC_1, MODA, input, X),O & (BC_1, MODB, input, X),O & (BC_1, MODC, input, X),O & (BC_1, MODD, input, X),O & (BC_6, D(23), bidir, X, 13, (BC_6, D(22), bidir, X, 13, (BC_6, D(21), bidir, X, 13, (BC_6, D(20), bidir, X, 13, (BC_6, D(19), bidir, X, 13, (BC_6, D(18), bidir, X, 13, (BC_6, D(17), bidir, X, 13, (BC_6, D(16), bidir, X, 13, (BC_6, D(15), bidir, X, 13, (BC_1, *, control, 1),O & (BC_6, D(14), bidir, X, 13, (BC_6, D(13), bidir, X, 13, (BC_6, D(12), bidir, X, 13, (BC_6, D(11), bidir, X, 26, (BC_6, D(10), bidir, X, 26, (BC_6, D(9), bidir, X, 26, cell port func safe [ccell dis (BC_6, D(8), bidir, X, 26, (BC_6, D(7), bidir, X, 26, (BC_6, D(6), bidir, X, 26, (BC_6, D(5), bidir, X, 26, (BC_6, D(4), bidir, X, 26, (BC_6, D(3), bidir, X, 26, (BC_1, *, control, 1),O & (BC_6, D(2), bidir, X, 26, rslt] 1, 1, 1, 1, 1, 1, 1, 1, 1, Z),O Z),O Z),O Z),O Z),O Z),O Z),O Z),O Z),O & & & & & & & & & & & & & & & & & & & & & 1, Z),O 1, Z),O 1, Z),O 1, Z),O 1, Z),O 1, Z),O rslt] 1, Z),O 1, Z),O 1, Z),O 1, Z),O 1, Z),O 1, Z),O 1, Z),O & C-12 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. DSP56309 BSDL Listing O28 O29 O30 O31 O32 O33 O34 O35 O36 O37 O38 O39 -- num O40 O41 O42 O43 O44 O45 O46 O47 O48 O49 O50 O51 O52 O53 O54 O55 O56 O57 O58 O59 -- num O60 O61 O62 O63 O64 O65 O66 O67 O68 O69 O70 O71 O72 O73 O74 O75 O76 O77 O78 (BC_6, (BC_6, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, cell (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_6, (BC_1, cell (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, D(1), bidir, D(0), bidir, A(17), output3, A(16), output3, A(15), output3, *, control, A(14), output3, A(13), output3, A(12), output3, A(11), output3, A(10), output3, A(9), output3, port func A(8), output3, A(7), output3, A(6), output3, *, control, A(5), output3, A(4), output3, A(3), output3, A(2), output3, A(1), output3, A(0), output3, BG_N, input, AA(0), output3, AA(1), output3, RD_N, output3, WR_N, output3, *, control, *, control, *, control, BB_N, bidir, BR_N, output2, port func TA_N, input, BCLK_N, output3, BCLK, output3, CLKOUT, output2, *, control, *, control, *, control, *, control, EXTAL, input, CAS_N, output3, AA(2), output3, AA(3), output3, RESET_N, input, *, control, HAD(0), bidir, *, control, HAD(1), bidir, *, control, HAD(2), bidir, X, 26, X, 26, X, 33, X, 33, X, 33, 1),O & X, 33, X, 33, X, 33, X, 33, X, 33, X, 33, safe [ccell dis X, 43, X, 43, X, 43, 1),O & X, 43, X, 43, X, 43, X, 43, X, 43, X, 43, X),O & X, 55, X, 56, X, 64, X, 64, 1),O & 1),O & 1),O & X, 57, X),O & safe [ccell dis X),O & X, 64, X, 64, X),O & 1),O & 1),O & 1),O & 1),O & X),O & X, 65, X, 66, X, 67, X),O & 1),O & X, 73, 1),O & X, 75, 1),O & X, 77, 1, 1, 1, 1, 1, Z),O Z),O Z),O Z),O Z),O & & & & & & & & & & & & & & & & & & & & & & & & Freescale Semiconductor, Inc... 1, Z),O 1, Z),O 1, Z),O 1, Z),O 1, Z),O 1, Z),O rslt] 1, Z),O 1, Z),O 1, Z),O 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, Z),O Z),O Z),O Z),O Z),O Z),O Z),O Z),O Z),O Z),O 1, Z),O & rslt] 1, 1, Z),O & Z),O & 1, 1, 1, Z),O & Z),O & Z),O & 1, 1, 1, Z),O & Z),O & Z),O & MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D C-13 Freescale Semiconductor, Inc. DSP56309 BSDL Listing O79 -- num O80 O81 O82 O83 O84 O85 O86 O87 O88 O89 O90 O91 O92 O93 O94 O95 O96 O97 O98 O99 -- num O100 O101 O102 O103 O104 O105 O106 O107 O108 O109 O110 O111 O112 O113 O114 O115 O116 O117 O118 O119 -- num O120 O121 O122 O123 O124 O125 O126 O127 O128 (BC_1, cell (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, cell (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, cell (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, *, control, port func HAD(3), bidir, *, control, HAD(4), bidir, *, control, HAD(5), bidir, *, control, HAD(6), bidir, *, control, HAD(7), bidir, *, control, HAS, bidir, *, control, HA8, bidir, *, control, HA9, bidir, *, control, HCS, bidir, *, control, TIO0, bidir, *, control, port func TIO1, bidir, *, control, TIO2, bidir, *, control, HREQ, bidir, *, control, HACK, bidir, *, control, HRW, bidir, *, control, HDS, bidir, *, control, SCK0, bidir, *, control, SCK1, bidir, *, control, SCLK, bidir, *, control, TXD, bidir, *, control, port func RXD, bidir, *, control, SC00, bidir, *, control, SC10, bidir, *, control, STD0, bidir, *, control, SRD0, bidir, 1),O & safe [ccell dis X, 79, 1),O & X, 81, 1),O & X, 83, 1),O & X, 85, 1),O & X, 87, 1),O & X, 89, 1),O & X, 91, 1),O & X, 93, 1),O & X, 95, 1),O & X, 97, 1),O & safe [ccell dis X, 99, 1),O & X, 101, 1),O & X, 103, 1),O & X, 105, 1),O & X, 107, 1),O & X, 109, 1),O & X, 111, 1),O & X, 113, 1),O & X, 115, 1),O & X, 117, 1),O & safe [ccell dis X, 119, 1),O & X, 121, 1),O & X, 123, 1),O & X, 125, 1),O & X, 127, rslt] 1, Z),O & 1, 1, 1, 1, 1, 1, 1, 1, 1, Z),O & Z),O & Z),O & Z),O & Z),O & Z),O & Z),O & Z),O & Z),O & Freescale Semiconductor, Inc... rslt] 1, Z),O & 1, 1, 1, 1, 1, 1, 1, 1, 1, Z),O & Z),O & Z),O & Z),O & Z),O & Z),O & Z),O & Z),O & Z),O & rslt] 1, Z),O & 1, 1, 1, 1, Z),O & Z),O & Z),O & Z),O & C-14 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. DSP56309 BSDL Listing Freescale Semiconductor, Inc... O129 O130 O131 O132 O133 O134 O135 O136 O137 O138 O139 -- num O140 O141 O142 O143 end DSP56309; (BC_1, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, cell (BC_1, (BC_6, (BC_1, (BC_6, PINIT, input, *, control, DE_N, bidir, *, control, SC01, bidir, *, control, SC02, bidir, *, control, STD1, bidir, *, control, SRD1, bidir, port func *, control, SC11, bidir, *, control, SC12, bidir, X),O & 1),O & X, 130, 1),O & X, 132, 1),O & X, 134, 1),O & X, 136, 1),O & X, 138, safe [ccell dis 1),O & X, 140, 1),O & X, 142, 1, 1, 1, 1, Pull1),O & Z),O & Z),O & Z),O & 1, Z),O & rslt] 1, 1, Z),O & Z)O; ---------------------------------------------------------------------- M O T O R O L A S S D T J T A G S O F T W A R E -- BSDL File Generated: Wed May 20 09:48:32 1998 --- Revision History: -entity DSP56309 is generic (PHYSICAL_PIN_MAP : string := OPBGA196O); port ( DE_N: SC02: SC01: SC00: STD0: SCK0: SRD0: SRD1: SCK1: STD1: SC10: SC11: SC12: TXD: SCLK: RXD: TIO0: TIO1: TIO2: HAD: HREQ: MODD: MODC: MODB: inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout in in in bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit_vector(0 to 7); bit; bit; bit; bit; MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D C-15 Freescale Semiconductor, Inc. DSP56309 BSDL Listing MODA: D: A: EXTAL: XTAL: RD_N: WR_N: AA: BR_N: BG_N: BB_N: PCAP: RESET_N: PINIT: TA_N: CAS_N: BCLK: BCLK_N: CLKOUT: TRST_N: TDO: TDI: TCK: TMS: RESERVED: SVCC: HVCC: DVCC: AVCC: HACK: HDS: HRW: CVCC: HCS: HA9: HA8: HAS: GND: QVCCL: QVCCH: PVCC: PGND: PGND1: in inout out in linkage out out out buffer in inout linkage in in in out out out buffer in out in in in linkage linkage linkage linkage linkage inout inout inout linkage inout inout inout inout linkage linkage linkage linkage linkage linkage bit; bit_vector(0 bit_vector(0 bit; bit; bit; bit; bit_vector(0 bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit_vector(0 bit_vector(0 bit; bit_vector(0 bit_vector(0 bit; bit; bit; bit_vector(0 bit; bit; bit; bit; bit_vector(0 bit_vector(0 bit_vector(0 bit; bit; bit); to 23); to 17); to 3); Freescale Semiconductor, Inc... to 4); to 1); to 3); to 2); to 1); to 63); to 3); to 2); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of DSP56309 : entity is OSTD_1149_1_1993O; attribute PIN_MAP of DSP56309 : entity is PHYSICAL_PIN_MAP; constant PBGA196 : PIN_MAP_STRING := ORESERVED: (A1, A14, B14, P1, P14), O & OSC11: A2, O & C-16 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. DSP56309 BSDL Listing OTMS: OTDO: OMODB: OD: A10, B9, O & A3, A4, A5, (E14, O& O& O& D12, D13, C13, C14, B13, C12, A13, B12, A12, B11, A11, C10, B10, Freescale Semiconductor, Inc... OA9, B8, C8, A8, B7, B6, C6, A6), O & ODVCC: (A7, C9, C11, D14), O & OSRD1: B1, O & OSC12: B2, O & OTDI: B3, O & OTRST_N: B4, O & OMODD: B5, O & OSC02: C1, O & OSTD1: C2, O & OTCK: C3, O & OMODA: C4, O & OMODC: C5, O & OQVCCL: (C7, G13, H2, N9), O & OPINIT: D1, O & OSC01: D2, O & ODE_N: D3, O & OGND: (E8, E9, E10, E11, F4, F5, F11, G4, G5, G6, G7, G8, G9, G10, G11, H4, H5, H6, O & OH7, H8, H9, H10, H11, J4, J5, J6, J7, J8, J9, J10, J11, K4, K5, K6, K7, K8, K9, O & OK10, K11, L4, L5, L6, L7, L8, L9, L10, L11, D4, D5, D6, D7, D8, D9, D10, D11, E4, O & OSTD0: OSVCC: OSRD0: OA: F13, F14, O & ORXD: OSC10: OSC00: OQVCCH: OSCK1: OSCLK: OTXD: OSCK0: OAVCC: OHACK: OHRW: OHDS: OHREQ: OTIO2: OHCS: OTIO1: OTIO0: OHA8: OHA9: OE13, E12), O & F1, O & F2, O & F3, O & (F12, H1, M7), O & G1, O & G2, O & G3, O & H3, O & (H12, K12, L12), O & J1, O & J2, O & J3, O & K2, O & K3, O & L1, O & L2, O & L3, O & M1, O & M2, O & OE5, E6, E1, (E2, E3, (N14, E7, F6, F7, F8, F9, F10), O & O& K1), O & O& M13, M14, L13, L14, K13, K14, J13, J12, J14, H13, H14, G14, G12, MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D C-17 Freescale Semiconductor, Inc. DSP56309 BSDL Listing Freescale Semiconductor, Inc... OHAS: OHVCC: OHAD: OPVCC: OEXTAL: OCLKOUT: OBCLK_N: OWR_N: ORD_N: ORESET_N: OPGND: OAA: OCAS_N: OBCLK: OBR_N: OCVCC: OPCAP: OPGND1: OXTAL: OTA_N: OBB_N: OBG_N: attribute attribute attribute attribute attribute M3, O & M4, O & (M5, P4, N4, P3, N3, P2, N1, N2), O & M6, O & M8, O & M9, O & M10, O & M11, O & M12, O & N5, O & N6, O & (N13, P12, P7, N7), O & N8, O & N10, O & N11, O & (N12, P9), O & P5, O & P6, O & P8, O & P10, O & P11, O & P13 O; of TDI : of TDO : of TMS : of TRST_N : of TCK : signal signal signal signal signal is is is is is true; true; true; true; (20.0e6, BOTH); TAP_SCAN_IN TAP_SCAN_OUT TAP_SCAN_MODE TAP_SCAN_RESET TAP_SCAN_CLOCK attribute INSTRUCTION_LENGTH of DSP56309 : entity is 4; attribute INSTRUCTION_OPCODE of DSP56309 : entity is OEXTEST (0000),O & OSAMPLE (0001),O & OIDCODE (0010),O & OCLAMP (0101),O & OHIGHZ (0100),O & OENABLE_ONCE (0110),O & ODEBUG_REQUEST (0111),O & OBYPASS (1111)O; attribute INSTRUCTION_CAPTURE of DSP56309 : entity is O0001O; attribute IDCODE_REGISTER of DSP56309 : entity is O0010O & -- version O000110O & -- manufacturerOs use O0000000010O & -- sequence number O00000001110O & -- manufacturer identity O1O; -- 1149.1 requirement attribute REGISTER_ACCESS of DSP56309 : entity is OONCE[8] (ENABLE_ONCE,DEBUG_REQUEST)O ; attribute BOUNDARY_LENGTH of DSP56309 : entity is 144; C-18 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. DSP56309 BSDL Listing attribute -- num O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O19 -- num O20 O21 O22 O23 O24 O25 O26 O27 O28 O29 O30 O31 O32 O33 O34 O35 O36 O37 O38 O39 -- num O40 O41 O42 O43 O44 O45 O46 O47 BOUNDARY_REGISTER of DSP56309 : entity is cell port func safe [ccell dis (BC_1, MODA, input, X),O & (BC_1, MODB, input, X),O & (BC_1, MODC, input, X),O & (BC_1, MODD, input, X),O & (BC_6, D(23), bidir, X, 13, (BC_6, D(22), bidir, X, 13, (BC_6, D(21), bidir, X, 13, (BC_6, D(20), bidir, X, 13, (BC_6, D(19), bidir, X, 13, (BC_6, D(18), bidir, X, 13, (BC_6, D(17), bidir, X, 13, (BC_6, D(16), bidir, X, 13, (BC_6, D(15), bidir, X, 13, (BC_1, *, control, 1),O & (BC_6, D(14), bidir, X, 13, (BC_6, D(13), bidir, X, 13, (BC_6, D(12), bidir, X, 13, (BC_6, D(11), bidir, X, 26, (BC_6, D(10), bidir, X, 26, (BC_6, D(9), bidir, X, 26, cell port func safe [ccell dis (BC_6, D(8), bidir, X, 26, (BC_6, D(7), bidir, X, 26, (BC_6, D(6), bidir, X, 26, (BC_6, D(5), bidir, X, 26, (BC_6, D(4), bidir, X, 26, (BC_6, D(3), bidir, X, 26, (BC_1, *, control, 1),O & (BC_6, D(2), bidir, X, 26, (BC_6, D(1), bidir, X, 26, (BC_6, D(0), bidir, X, 26, (BC_1, A(17), output3, X, 33, (BC_1, A(16), output3, X, 33, (BC_1, A(15), output3, X, 33, (BC_1, *, control, 1),O & (BC_1, A(14), output3, X, 33, (BC_1, A(13), output3, X, 33, (BC_1, A(12), output3, X, 33, (BC_1, A(11), output3, X, 33, (BC_1, A(10), output3, X, 33, (BC_1, A(9), output3, X, 33, cell port func safe [ccell dis (BC_1, A(8), output3, X, 43, (BC_1, A(7), output3, X, 43, (BC_1, A(6), output3, X, 43, (BC_1, *, control, 1),O & (BC_1, A(5), output3, X, 43, (BC_1, A(4), output3, X, 43, (BC_1, A(3), output3, X, 43, (BC_1, A(2), output3, X, 43, rslt] Freescale Semiconductor, Inc... 1, 1, 1, 1, 1, 1, 1, 1, 1, Z),O Z),O Z),O Z),O Z),O Z),O Z),O Z),O Z),O & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & 1, Z),O 1, Z),O 1, Z),O 1, Z),O 1, Z),O 1, Z),O rslt] 1, Z),O 1, Z),O 1, Z),O 1, Z),O 1, Z),O 1, Z),O 1, 1, 1, 1, 1, 1, Z),O Z),O Z),O Z),O Z),O Z),O 1, Z),O 1, Z),O 1, Z),O 1, Z),O 1, Z),O 1, Z),O rslt] 1, Z),O 1, Z),O 1, Z),O 1, 1, 1, 1, Z),O Z),O Z),O Z),O MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D C-19 Freescale Semiconductor, Inc. DSP56309 BSDL Listing O48 O49 O50 O51 O52 O53 O54 O55 O56 O57 O58 O59 -- num O60 O61 O62 O63 O64 O65 O66 O67 O68 O69 O70 O71 O72 O73 O74 O75 O76 O77 O78 O79 -- num O80 O81 O82 O83 O84 O85 O86 O87 O88 O89 O90 O91 O92 O93 O94 O95 O96 O97 O98 (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_6, (BC_1, cell (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, cell (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, A(1), output3, A(0), output3, BG_N, input, AA(0), output3, AA(1), output3, RD_N, output3, WR_N, output3, *, control, *, control, *, control, BB_N, bidir, BR_N, output2, port func TA_N, input, BCLK_N, output3, BCLK, output3, CLKOUT, output2, *, control, *, control, *, control, *, control, EXTAL, input, CAS_N, output3, AA(2), output3, AA(3), output3, RESET_N, input, *, control, HAD(0), bidir, *, control, HAD(1), bidir, *, control, HAD(2), bidir, *, control, port func HAD(3), bidir, *, control, HAD(4), bidir, *, control, HAD(5), bidir, *, control, HAD(6), bidir, *, control, HAD(7), bidir, *, control, HAS, bidir, *, control, HA8, bidir, *, control, HA9, bidir, *, control, HCS, bidir, *, control, TIO0, bidir, X, 43, X, 43, X),O & X, 55, X, 56, X, 64, X, 64, 1),O & 1),O & 1),O & X, 57, X),O & safe [ccell dis X),O & X, 64, X, 64, X),O & 1),O & 1),O & 1),O & 1),O & X),O & X, 65, X, 66, X, 67, X),O & 1),O & X, 73, 1),O & X, 75, 1),O & X, 77, 1),O & safe [ccell dis X, 79, 1),O & X, 81, 1),O & X, 83, 1),O & X, 85, 1),O & X, 87, 1),O & X, 89, 1),O & X, 91, 1),O & X, 93, 1),O & X, 95, 1),O & X, 97, 1, 1, 1, 1, 1, 1, Z),O & Z),O & Z),O Z),O Z),O Z),O & & & & 1, Z),O & rslt] 1, 1, Z),O & Z),O & Freescale Semiconductor, Inc... 1, 1, 1, Z),O & Z),O & Z),O & 1, 1, 1, Z),O & Z),O & Z),O & rslt] 1, Z),O & 1, 1, 1, 1, 1, 1, 1, 1, 1, Z),O & Z),O & Z),O & Z),O & Z),O & Z),O & Z),O & Z),O & Z),O & C-20 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. DSP56309 BSDL Listing O99 -- num O100 O101 O102 O103 O104 O105 O106 O107 O108 O109 O110 O111 O112 O113 O114 O115 O116 O117 O118 O119 -- num O120 O121 O122 O123 O124 O125 O126 O127 O128 O129 O130 O131 O132 O133 O134 O135 O136 O137 O138 O139 -- num O140 O141 O142 O143 end DSP56309; (BC_1, cell (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, cell (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, cell (BC_1, (BC_6, (BC_1, (BC_6, *, control, port func TIO1, bidir, *, control, TIO2, bidir, *, control, HREQ, bidir, *, control, HACK, bidir, *, control, HRW, bidir, *, control, HDS, bidir, *, control, SCK0, bidir, *, control, SCK1, bidir, *, control, SCLK, bidir, *, control, TXD, bidir, *, control, port func RXD, bidir, *, control, SC00, bidir, *, control, SC10, bidir, *, control, STD0, bidir, *, control, SRD0, bidir, PINIT, input, *, control, DE_N, bidir, *, control, SC01, bidir, *, control, SC02, bidir, *, control, STD1, bidir, *, control, SRD1, bidir, port func *, control, SC11, bidir, *, control, SC12, bidir, 1),O & safe [ccell dis X, 99, 1),O & X, 101, 1),O & X, 103, 1),O & X, 105, 1),O & X, 107, 1),O & X, 109, 1),O & X, 111, 1),O & X, 113, 1),O & X, 115, 1),O & X, 117, 1),O & safe [ccell dis X, 119, 1),O & X, 121, 1),O & X, 123, 1),O & X, 125, 1),O & X, 127, X),O & 1),O & X, 130, 1),O & X, 132, 1),O & X, 134, 1),O & X, 136, 1),O & X, 138, safe [ccell dis 1),O & X, 140, 1),O & X, 142, rslt] 1, Z),O & 1, 1, 1, 1, 1, 1, 1, 1, 1, Z),O & Z),O & Z),O & Z),O & Z),O & Z),O & Z),O & Z),O & Z),O & Freescale Semiconductor, Inc... rslt] 1, Z),O & 1, 1, 1, 1, Z),O & Z),O & Z),O & Z),O & 1, 1, 1, 1, Pull1),O & Z),O & Z),O & Z),O & 1, Z),O & rslt] 1, 1, Z),O & Z)O; MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D C-21 Freescale Semiconductor, Inc. DSP56309 BSDL Listing Freescale Semiconductor, Inc... C-22 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. APPENDIX D PROGRAMMING REFERENCE Freescale Semiconductor, Inc... MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D D-1 Freescale Semiconductor, Inc. Programming Reference D.1 D.2 D.3 D.4 D.5 Freescale Semiconductor, Inc... INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3 INTERNAL I/O MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . D-4 INTERRUPT ADDRESSES AND SOURCES . . . . . . . . . . . D-11 INTERRUPT PRIORITIES. . . . . . . . . . . . . . . . . . . . . . . . . . D-13 PROGRAMMING REFERENCE: CENTRAL PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . D-15 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-19 HOST INTERFACE (HI08) . . . . . . . . . . . . . . . . . . . . . . . . . D-20 ENHANCED SYNCHRONOUS SERIAL INTERFACE (ESSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-26 SERIAL COMMUNICATIONS INTERFACE . . . . . . . . . . . . D-30 TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-33 GENERAL PURPOSE I/O (GPIO). . . . . . . . . . . . . . . . . . . . D-36 D-2 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. PERIPHERAL ADDRESSES Programming Reference D.1 INTRODUCTION Freescale Semiconductor, Inc... This section has been compiled as a reference for programmers. It contains a table showing the addresses of all the DSPOs memory-mapped peripherals, an exception priority table, and programming sheets for the major programmable registers on the DSP. The programming sheets are grouped in the following order: central processor, Phase-Locked Loop (PLL), Host Interface (HI08), Enhanced Synchronous Serial Interface (ESSI), Serial Communication Interface (SCI), Timer, and GPIO. Each sheet provides room to write in the value of each bit and the hexadecimal value for each register. The programmer can photocopy these sheets and reuse them for each application development project. For details about the instruction set of the DSP56300 family chips, see the DSP56300 Family Manual. D.1.1 Peripheral Addresses Table D-1 lists the memory addresses of all on-chip peripherals. D.1.2 Interrupt Addresses Table D-2 on page -11 lists the interrupt starting addresses and sources. D.1.3 Interrupt Priorities Table D-3 on page -13 lists the priorities of specific interrupts within interrupt priority levels. D.1.4 Programming Sheets The remaining figures show the major programmable registers on the DSP56309. MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D D-3 Freescale Semiconductor, Inc. Programming Reference D.2 INTERNAL I/O MEMORY MAP Table D-1 Internal I/O Memory Map Peripheral IPR 16-Bit Address $FFFF $FFFE 24-Bit Address $FFFFFF $FFFFFE $FFFFFD $FFFFFC $FFFFFB $FFFFFA $FFFFF9 $FFFFF8 $FFFFF7 $FFFFF6 $FFFFF5 $FFFFF4 $FFFFF3 $FFFFF2 $FFFFF1 $FFFFF0 $FFFFEF $FFFFEE $FFFFED $FFFFEC Register Name Interrupt Priority Register Core (IPR-C) Interrupt Priority Register Peripheral (IPR-P) PLL Control Register (PCTL) OnCE GDB Register (OGDB) Bus Control Register (BCR) DRAM Control Register (DCR) Address Attribute Register 0 (AAR0) Address Attribute Register 1 (AAR1) Address Attribute Register 2 (AAR2) Address Attribute Register 3 (AAR3) ID Register (IDR) DMA Status Register (DSTR) DMA Offset Register 0 (DOR0) DMA Offset Register 1 (DOR1) DMA Offset Register 2 (DOR2) DMA Offset Register 3 (DOR3) DMA Source Address Register (DSR0) DMA Destination Address Register (DDR0) DMA Counter (DCO0) DMA Control Register (DCR0) PLL $FFFD $FFFC $FFFB $FFFA $FFF9 $FFF8 $FFF7 $FFF6 $FFF5 Freescale Semiconductor, Inc... OnCE BIU DMA $FFF4 $FFF3 $FFF2 $FFF1 $FFF0 DMA0 $FFEF $FFEE $FFED $FFEC D-4 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Programming Reference Table D-1 Internal I/O Memory Map (Continued) Peripheral DMA1 16-Bit Address $FFEB $FFEA $FFE9 $FFE8 24-Bit Address $FFFFEB $FFFFEA $FFFFE9 $FFFFE8 $FFFFE7 $FFFFE6 $FFFFE5 $FFFFE4 $FFFFE3 $FFFFE2 $FFFFE1 $FFFFE0 $FFFFDF $FFFFDE $FFFFDD $FFFFDC $FFFFDB $FFFFDA $FFFFD9 $FFFFD8 Register Name DMA Source Address Register (DSR1) DMA Destination Address Register (DDR1) DMA Counter (DCO1) DMA Control Register (DCR1) DMA Source Address Register (DSR2) DMA Destination Address Register (DDR2) DMA Counter (DCO2) DMA Control Register (DCR2) DMA Source Address Register (DSR3) DMA Destination Address Register (DDR3) DMA Counter (DCO3) DMA Control Register (DCR3) DMA Source Address Register (DSR4) DMA Destination Address Register (DDR4) DMA Counter (DCO4) DMA Control Register (DCR4) DMA Source Address Register (DSR5) DMA Destination Address Register (DDR5) DMA Counter (DCO5) DMA Control Register (DCR5) Freescale Semiconductor, Inc... DMA2 $FFE7 $FFE6 $FFE5 $FFE4 DMA3 $FFE3 $FFE2 $FFE1 $FFE0 DMA4 $FFDF $FFDE $FFDD $FFDC DMA5 $FFDB $FFDA $FFD9 $FFD8 MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D D-5 Freescale Semiconductor, Inc. Programming Reference Table D-1 Internal I/O Memory Map (Continued) Peripheral N 16-Bit Address $FFD7 $FFD6 $FFD5 $FFD4 24-Bit Address $FFFFD7 $FFFFD6 $FFFFD5 $FFFFD4 $FFFFD3 $FFFFD2 $FFFFD1 $FFFFD0 $FFFFCF $FFFFCE $FFFFCD $FFFFCC $FFFFCB $FFFFCA $FFFFC9 $FFFFC8 $FFFFC7 $FFFFC6 $FFFFC5 $FFFFC4 $FFFFC3 $FFFFC2 $FFFFC1 $FFFFC0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Host Port GPIO Data Register (HDR) Host Port GPIO Direction Register (HDDR) Host Transmit Register (HTX) Host Receive Register (HRX) Host Base Address Register (HBAR) Host Polarity Control Register (HPCR) Host Status Register (HSR) Host Control Register (HCR) Reserved Reserved Register Name Freescale Semiconductor, Inc... $FFD3 $FFD2 $FFD1 $FFD0 N $FFCF $FFCE $FFCD $FFCC $FFCB $FFCA PORT B $FFC9 $FFC8 HI08 $FFC7 $FFC6 $FFC5 $FFC4 $FFC3 $FFC2 $FFC1 $FFC0 D-6 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Programming Reference Table D-1 Internal I/O Memory Map (Continued) Peripheral PORT C 16-Bit Address $FFBF $FFBE $FFBD ESSI 0 $FFBC $FFBB $FFBA $FFB9 $FFB8 $FFB7 $FFB6 $FFB5 $FFB4 $FFB3 $FFB2 $FFB1 N PORT D $FFB0 $FFAF $FFAE $FFAD 24-Bit Address $FFFFBF $FFFFBE $FFFFBD $FFFFBC $FFFFBB $FFFFBA $FFFFB9 $FFFFB8 $FFFFB7 $FFFFB6 $FFFFB5 $FFFFB4 $FFFFB3 $FFFFB2 $FFFFB1 $FFFFB0 $FFFFAF $FFFFAE $FFFFAD Register Name Port C Control Register (PCRC) Port C Direction Register (PRRC) Port C GPIO Data Register (PDRC) ESSI 0 Transmit Data Register 0 (TX00) ESSI 0 Transmit Data Register 1 (TX01) ESSI 0 Transmit Data Register 2 (TX02) ESSI 0 Time Slot Register (TSR0) ESSI 0 Receive Data Register (RX0) ESSI 0 Status Register (SSISR0) ESSI 0 Control Register B (CRB0) ESSI 0 Control Register A (CRA0) ESSI 0 Transmit Slot Mask Register A (TSMA0) ESSI 0 Transmit Slot Mask Register B (TSMB0) ESSI 0 Receive Slot Mask Register A (RSMA0) ESSI 0 Receive Slot Mask Register B (RSMB0) Reserved Port D Control Register (PCRD) Port D Direction Register (PRRD) Port C GPIO Data Register (PDRD) Freescale Semiconductor, Inc... MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D D-7 Freescale Semiconductor, Inc. Programming Reference Table D-1 Internal I/O Memory Map (Continued) Peripheral ESSI 1 16-Bit Address $FFAC $FFAB $FFAA $FFA9 24-Bit Address $FFFFAC $FFFFAB $FFFFAA $FFFFA9 $FFFFA8 $FFFFA7 $FFFFA6 $FFFFA5 $FFFFA4 $FFFFA3 $FFFFA2 $FFFFA1 $FFFFA0 $FFFF9F $FFFF9E $FFFF9D Register Name ESSI 1 Transmit Data Register 0 (TX10) ESSI 1 Transmit Data Register 1 (TX11) ESSI 1 Transmit Data Register 2 (TX12) ESSI 1 Time Slot Register (TSR1) ESSI 1 Receive Data Register (RX1) ESSI 1 Status Register (SSISR1) ESSI 1 Control Register B (CRB1) ESSI 1 Control Register A (CRA1) ESSI 1 Transmit Slot Mask Register A (TSMA1) ESSI 1 Transmit Slot Mask Register B (TSMB1) ESSI 1 Receive Slot Mask Register A (RSMA1) ESSI 1 Receive Slot Mask Register B (RSMB1) Reserved Port E Control Register (PCRE) Port E Direction Register (PRRE) Port E GPIO Data Register (PDRE) Freescale Semiconductor, Inc... $FFA8 $FFA7 $FFA6 $FFA5 $FFA4 $FFA3 $FFA2 $FFA1 N PORT E $FFA0 $FF9F $FF9E $FF9D D-8 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Programming Reference Table D-1 Internal I/O Memory Map (Continued) Peripheral SCI 16-Bit Address $FF9C $FF9B $FF9A $FF99 24-Bit Address $FFFF9C $FFFF9B $FFFF9A $FFFF99 $FFFF98 $FFFF97 $FFFF96 $FFFF95 $FFFF94 $FFFF93 $FFFF92 $FFFF91 $FFFF90 Register Name SCI Control Register (SCR) SCI Clock Control Register (SCCR) SCI Receive Data Register - High (SRXH) SCI Receive Data Register - Middle (SRXM) SCI Recieve Data Register - Low (SRXL) SCI Transmit Data Register - High (STXH) SCI Transmit Data Register - Middle (STXM) SCI Transmit Data Register - Low (STXL) SCI Transmit Address Register (STXA) SCI Status Register (SSR) Reserved Reserved Reserved Freescale Semiconductor, Inc... $FF98 $FF97 $FF96 $FF95 $FF94 $FF93 N $FF92 $FF91 $FF90 MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D D-9 Freescale Semiconductor, Inc. Programming Reference Table D-1 Internal I/O Memory Map (Continued) Peripheral TRIPLE TIMER 16-Bit Address $FF8F $FF8E $FF8D $FF8C 24-Bit Address $FFFF8F $FFFF8E $FFFF8D $FFFF8C $FFFF8B $FFFF8A $FFFF89 $FFFF88 $FFFF87 $FFFF86 $FFFF85 $FFFF84 $FFFF83 $FFFF82 $FFFF81 $FFFF80 Register Name Timer 0 Control/Status Register (TCSR0) Timer 0 Load Register (TLR0) Timer 0 Compare Register (TCPR0) Timer 0 Count Register (TCR0) Timer 1 Control/Status Register (TCSR1) Timer 1 Load Register (TLR1) Timer 1 Compare Register (TCPR1) Timer 1 Count Register (TCR1) Timer 2 Control/Status Register (TCSR2) Timer 2 Load Register (TLR2) Timer 2 Compare Register (TCPR2) Timer 2 Count Register (TCR2) Timer Prescaler Load Register (TPLR) Timer Prescaler Count Register (TPCR) Reserved Reserved Freescale Semiconductor, Inc... $FF8B $FF8A $FF89 $FF88 $FF87 $FF86 $FF85 $FF84 $FF83 $FF82 N $FF81 $FF80 D-10 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Programming Reference D.3 INTERRUPT ADDRESSES AND SOURCES Table D-2 Interrupt Sources Interrupt Starting Address VBA:$00 Interrupt Priority Level Range 3 3 3 3 3 3 3 3 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 Hardware RESET Stack Error Illegal Instruction Debug Request Interrupt Trap Non-Maskable Interrupt (NMI) Reserved Reserved IRQA IRQB IRQC IRQD DMA Channel 0 DMA Channel 1 DMA Channel 2 DMA Channel 3 DMA Channel 4 DMA Channel 5 TIMER 0 Compare TIMER 0 Overflow TIMER 1 Compare TIMER 1 Overflow TIMER 2 Compare TIMER 2 Overflow ESSI0 Receive Data ESSI0 Receive Data With Exception Status ESSI0 Receive Last Slot ESSI0 Transmit Data Interrupt Source Freescale Semiconductor, Inc... VBA:$02 VBA:$04 VBA:$06 VBA:$08 VBA:$0A VBA:$0C VBA:$0E VBA:$10 VBA:$12 VBA:$14 VBA:$16 VBA:$18 VBA:$1A VBA:$1C VBA:$1E VBA:$20 VBA:$22 VBA:$24 VBA:$26 VBA:$28 VBA:$2A VBA:$2C VBA:$2E VBA:$30 VBA:$32 VBA:$34 VBA:$36 MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D D-11 Freescale Semiconductor, Inc. Programming Reference Table D-2 Interrupt Sources (Continued) Interrupt Starting Address VBA:$38 VBA:$3A VBA:$3C VBA:$3E VBA:$40 VBA:$42 VBA:$44 VBA:$46 VBA:$48 VBA:$4A VBA:$4C VBA:$4E VBA:$50 VBA:$52 VBA:$54 VBA:$56 VBA:$58 VBA:$5A VBA:$5C VBA:$5E VBA:$60 VBA:$62 VBA:$64 VBA:$66 : VBA:$FE Interrupt Priority Level Range 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 : 02 Interrupt Source ESSI0 Transmit Data With Exception Status ESSI0 Transmit Last Slot Reserved Reserved ESSI1 Receive Data ESSI1 Receive Data With Exception Status ESSI1 Receive Last Slot ESSI1 Transmit Data ESSI1 Transmit Data With Exception Status ESSI1 Transmit Last Slot Reserved Reserved SCI Receive Data SCI Receive Data With Exception Status SCI Transmit Data SCI Idle Line SCI Timer Reserved Reserved Reserved Host Receive Data Full Host Transmit Data Empty Host Command (Default) Reserved : Reserved Freescale Semiconductor, Inc... D-12 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Programming Reference D.4 INTERRUPT PRIORITIES Table D-3 Interrupt Source Priorities within an IPL Priority Interrupt Source Level 3 (Nonmaskable) Highest Hardware RESET Stack Error Illegal Instruction Debug Request Interrupt Trap Non-Maskable Interrupt Levels 0, 1, 2 (Maskable) Highest N N N N N N N N N N N N N IRQA (External Interrupt) IRQB (External Interrupt) IRQC (External Interrupt) IRQD (External Interrupt) DMA Channel 0 Interrupt DMA Channel 1 Interrupt DMA Channel 2 Interrupt DMA Channel 3 Interrupt DMA Channel 4 Interrupt DMA Channel 5 Interrupt Host Command Interrupt Host Transmit Data Empty Host Receive Data Full ESSI0 RX Data with Exception Interrupt Freescale Semiconductor, Inc... N N N N Lowest MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D D-13 Freescale Semiconductor, Inc. Programming Reference Table D-3 Interrupt Source Priorities within an IPL (Continued) Priority N N N N Interrupt Source ESSI0 RX Data Interrupt ESSI0 Receive Last Slot Interrupt ESSI0 TX Data With Exception Interrupt ESSI0 Transmit Last Slot Interrupt ESSI0 TX Data Interrupt ESSI1 RX Data With Exception Interrupt ESSI1 RX Data Interrupt ESSI1 Receive Last Slot Interrupt ESSI1 TX Data With Exception Interrupt ESSI1 Transmit Last Slot Interrupt ESSI1 TX Data Interrupt SCI Receive Data With Exception Interrupt SCI Receive Data SCI Transmit Data SCI Idle Line SCI Timer TIMER0 Overflow Interrupt TIMER0 Compare Interrupt TIMER1 Overflow Interrupt TIMER1 Compare Interrupt TIMER2 Overflow Interrupt TIMER2 Compare Interrupt Freescale Semiconductor, Inc... N N N N N N N N N N N N N N N N N Lowest D-14 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Programming Reference Application: Date: Programmer: Sheet 1 of 5 Central Processor Unnormalized ( U = Acc(47) xnor Acc(46) ) Extension Limit FFT Scaling ( S = Acc(46) xor Acc(45) ) Carry Overow Zero Negative Freescale Semiconductor, Inc... Scaling Mode S(1:0) Scaling Mode 00 No scaling 01 Scale down 10 Scale up 11 Reserved I(1:0) 00 01 10 11 Interrupt Mask Exceptions Masked None IPL 0 IPL 0, 1 IPL 0, 1, 2 Reserved Sixteen-Bit Compatibilitity Double Precision Multiply Mode Loop Flag DO-Forever Flag Sixteenth-Bit Arithmetic Reserved Instruction Cache Enable Arithmetic Saturation Rounding Mode Core Priority CP(1:0) Core Priority 00 0 (lowest) 01 1 10 2 11 3 (highest) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 CP1 CP0 RM SM CE 8 I0 7 S 6 L 5 E 4 U 3 N 2 Z 1 V 0 C * 0 SA FV LF DM SC * 0 S1 S0 I1 Extended Mode Register (MR) Mode Register (MR) Condition Code Register (CCR) Status Register (SR) Read/Write Reset = $C00300 *= Reserved, Program as 0 Figure D-1 Status Register (SR) MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D D-15 Freescale Semiconductor, Inc. Programming Reference Application: Date: Programmer: Sheet 2 of 5 Central Processor Chip Operating Modes MOD(D:A) Reset Vector Description 0000 $C00000 Expanded mode X001 $FF0000 Bootstrap from byte wide memory X010 $FF0000 Bootstrap through SCI X011 N Reserved X100 $FF0000 Host Bootstrap PCI mode (32-bit wide) X101 $FF0000 Host Bootstrap 16-bit wide UB mode (ISA) X110 $FF0000 Host Bootstrap 8-bit wide UB mode (dbl strb) X111 $FF0000 Host Bootstrap 8-bit wide UB mode (sgl strb) 1000 $008000 Expanded mode Freescale Semiconductor, Inc... External Bus Disable Stop Delay Memory Switch Mode CDP(1:0) 00 01 10 11 Core-DMA Priority Core-DMA Priority Core vs DMA Priority DMA accesses > Core DMA accesses = Core DMA accesses < Core Burst Mode Enable TA Synchronize Select Bus Release Timing Stack Extension Space Select Extended Stack Underflow Flag Extended Stack Overflow Flag Extended Stack Wrap Flag Stack Extension Enable 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 SD 5 4 3 2 MC 1 MB 0 MA *** 000 SEN WRP EOV EUN XYS *** 000 BRT TAS BE CDP1 CDP0 MS * 0 EBD MD System Stack Control Status Register (SCS) Extended Chip Operating Mode Register (COM) Chip Operating Mode Register (COM) Operating Mode Register (OMR) Read/Write Reset = $00030X * = Reserved, Program as 0 X = Latched from levels on Mode pins Figure D-2 Operating Mode Register (OMR) D-16 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc... Application: MOTOROLA IRQC Mode Trigger Level Neg. Edge ICL1 0 0 1 1 ICL0 0 1 0 1 Enabled No Yes Yes Yes IPL N 0 1 2 IAL1 0 0 1 1 IAL0 0 1 0 1 Enabled No Yes Yes Yes IAL2 0 1 Trigger Level Neg. Edge CENTRAL PROCESSOR IRQA Mode IPL N 0 1 2 ICL2 0 1 IRQD Mode IDL1 0 0 1 1 IDL0 0 1 0 1 Enabled No Yes Yes Yes IPL N 0 1 2 IBL2 0 1 Trigger Level Neg. Edge IBL1 0 0 1 1 IRQB Mode IBL0 0 1 0 1 Enabled No Yes Yes Yes IPL N 0 1 2 Freescale Semiconductor, Inc. Figure D-3 Interrupt Priority RegisterCore (IPRC) For More Information On This Product, Go to: www.freescale.com 23 22 21 20 19 18 17 16 15 14 13 12 11 10 D5L1 D5L0 D4L1 D4L0 D3L1 D3L0 D2L1 D2L0 D1L1 D1L0 D0L1 D0L0 IDL2 IDL1 DSP56309UM/D 9 8 7 IDL2 0 1 Trigger Level Neg. Edge Date: 6 5 IDL0 ICL2 ICL1 ICL0 IBL2 4 IBL1 3 IBL0 2 IAL2 1 IAL1 0 IAL0 Programmer: Interrupt Priority Register (IPRC) X:$FFFF Read/Write Reset = $000000 Sheet 3 of 5 Programming Reference D-17 Freescale Semiconductor, Inc... D-18 Application: ESSI1 IPL S1L1 S1L0 Enabled 0 0 No 0 1 Yes 1 0 Yes 1 1 Yes IPL N 0 1 2 HPL1 HPL0 Enabled 0 0 No 0 1 Yes 1 0 Yes 1 1 Yes IPL N 0 1 2 CENTRAL PROCESSOR Host IPL Programming Reference SCI IPL SCL1 0 0 1 1 SCL0 0 1 0 1 Enabled No Yes Yes Yes IPL N 0 1 2 ESSI0 IPL S0L1 S0L0 Enabled 0 0 No 0 1 Yes 1 0 Yes 1 1 Yes IPL N 0 1 2 Freescale Semiconductor, Inc. Figure D-4 Interrupt Priority Register Peripherals (IPRP) For More Information On This Product, Go to: www.freescale.com 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 DSP56309UM/D Date: 2 1 0 T0L1 T0L0 SCL1 SCL0 S1L1 S1L0 SOL1 S0L0 HPL1 HPL0 Programmer: Interrupt Priority Register (IPRP) X:$FFFF Read/Write Reset = $000000 ************** 00000000000000 $0 $0 $0 Sheet 4 of 5 MOTOROLA * = Reserved, Program as 0 Freescale Semiconductor, Inc... Application: MOTOROLA XTAL Disable Bit (XTLD) 0 = Enable Xtal Oscillator 1 = EXTAL Driven From An External Source Crystal Range Bit (XTLR) 0 = External Xtal Freq > 200KHz 1 = External Xtal Freq < 200KHz Multiplication Factor Bits MF0 MF11 MF11 MF0 Multiplication Factor MF $000 1 $001 2 $002 3 $FFF 4095 $FFF 4096 PLL PSTP and PEN Relationship Operation During STOP PSTP PEN PLL Oscillator 0 1 Disabled Disabled 1 0 Disabled Enabled 1 1 Enabled Enabled Freescale Semiconductor, Inc. Figure D-5 Phase-Locked Loop Control Register (PCTL) For More Information On This Product, Go to: www.freescale.com Division Factor Bits (DF0 DF2) DF2 DF0 Division Factor DF 20 $0 $1 21 $2 22 $7 27 Clock Output Disable (COD) 0 = 50% Duty Cycle Clock 1 = Pin Held In High State DSP56309UM/D 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 PD3 PD2 PD1 PD0 COD PEN PSTP XTLD XTLR DF2 DF1 Predivision Factor Bits (PD0 PD3) PD3 PD0 Predivision Factor PDF $0 1 $1 2 $2 3 $F 16 Date: Programmer: 8 DF0 MF11 MF10 MF9 MF8 7 6 5 4 3 2 MF7 MF6 MF5 MF4 MF3 MF2 1 0 MF1 MF0 Sheet 5 of 5 Programming Reference PLL Control Register (PCTL) X:$FFFFFD Read/Write Reset = $000000 D-19 Freescale Semiconductor, Inc. Programming Reference Application: Date: Programmer: Sheet 1 of 6 HOST Host Receive Data (usually Read by program) Freescale Semiconductor, Inc... 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Receive High Byte Receive Middle Byte 8 7 6 5 4 3 2 1 0 Receive Low Byte Host Receive Data Register (HRX) X:$FFEC6 Read Only Reset = empty Host Transmit Data (usually Loaded by program) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Transmit High Byte Transmit Middle Byte 8 7 6 5 4 3 2 1 0 Transmit Low Byte Host Transmit Data Register (HTX) X:$FFEC7 Write Only Reset = empty Figure D-6 Host Receive and Host Transmit Data Registers D-20 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Programming Reference Application: Date: Programmer: Sheet 2 of 6 HOST Host Receive Interrupt Enable 0 = Disable 1 = Enable if HRDF = 1 Host Transmit Interrupt Enable 0 = Disable 1 = Enable if HTDE = 1 Freescale Semiconductor, Inc... Host Command Interrupt Enable 0 = Disable 1 = Enable if HCP = 1 Host Flag 2 Host Flag 3 15 7 Host Control Register (HCR) X:$FFFFC2 Read /Write Reset = $0 6 5 4 HF3 3 HF2 2 1 0 HRIE *** * 000 0 HCIE HTIE DSP Side Host Receive Data Full 0 = Wait 1 = Read Host Transmit Data Empty 0 = Wait 1 = Write Host Command Pending 0 = Wait 1 = Ready Host Flags Read Only 15 7 Host Staus Register (HSR) X:$FFFFC3 Read Only Reset = $2 6 5 4 HF1 3 HF0 2 1 0 *** * 000 0 HCP HTDE HRDF *= Reserved, Program as 0 Figure D-7 Host Control and Host Status Registers MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D D-21 Freescale Semiconductor, Inc. Programming Reference Application: Date: Programmer: Sheet 3 of 6 HOST 15 Host Base Address Register (HBAR) X:$FFFFC5 Reset = $80 8 7 BA10 6 BA9 5 BA8 4 BA7 3 BA6 2 BA5 1 BA4 0 BA3 ** 00 Freescale Semiconductor, Inc... Host Request Open Drain HDRQ HROD HREN/HEW 0 0 1 0 1 1 1 0 1 1 1 1 Host Data Strobe Polarity 0 = Strobe Active Low, 1 = Strobe Active High Host Address Strobe Polarity 0 = Strobe Active Low, 1 = Strobe Active High Host Multiplexed Bus 0 = Nonmultiplexed, 1 = Multiplexed Host Dual Data Strobe 0 = Singles Stroke, 1 = Dual Stoke Host Chip Select Polarity 0 = HCS Active Low HTRQ & HRRQ Enable 1 = HCS Active High HDRQ 0 0 1 1 Host Request Priority HRP 0 HREQ Active Low 1 HREQ Active High 0 HTRQ,HRRQ Active Low 1 HTRQ,HRRQ Active High Host GPIO Port Enable 0 = GPIO Pins Disable, 1 = GPIO Pin Enable Host Address Line 8 Enable 0 (R) HA8 = GPIO, 1 (R) HA8 = HA8 Host Address Line 9 Enable 0 (R) HA9 = GPIO, 1 (R) HA9 = HA9 Host Chip Select Enable 0 (R) HCS/HAI0 = GPIO, 1 (R) HCS/HA10 = HC8, if HMUX = 0 1 (R) HCS/HA10 = HC10, if HMUX = 1 Host Request Enable 0 (R) HREQ/HACK = GPIO, 1 (R) HREQ = HREQ, if HDRQ = 0 Host Acknowledge Enable 0 (R) HACK = GPIO If HDRQ & HREN = 1, HACK = HACK Host Enable 0 (R) HI08 Disable Pins = GPIO 1 (R) HI08 Enable Host Acknowledge Priority 0 = HACK Active Low, 1 = HACK Active High 15 Host Port Control Register (HPCR) X:$FFFFC4 Read/Write Reset = $0 HAP 14 HRP 13 HCSP 12 11 10 HASP 9 HDSP 8 HROD 7 6 HEN 5 HAEN 4 3 2 1 0 HDDS HMUX * 0 HREN HCSEN HA9EN HA8EN HGEN * = Reserved, Program as 0 Figure D-8 Host Base Address and Host Port Control Registers D-22 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Programming Reference Application: Date: Programmer: Sheet 4 of 6 HOST Processor Side Receive Request Enable DMA Off 0 = Interrupts Disabled DMA On 0 = Host (R) DSP Transmit Request Enable DMA Off 0 = O Interrupts Disabled DMA On 0 = DSP (R) Host HDRQ HREQ/HTRQ HACK/HRRQ 0 HREQ HACK 1 HTRQ HRRQ Host Flags Write Only Host Little Endian Initialize (Write Only) 0 = No Action 1 = Initialize DMA 1 = Interrupts Enabled 1 = DSP (R) Host 1 = Interrupts Enabled 1 = Host (R) DSP Freescale Semiconductor, Inc... 7 INIT 6 5 HLEND 4 HF1 3 HF0 2 1 0 Interrupt Control Register (ICR) X:$ Read/Write Reset = $0 * 0 HDRQ TREQ RREQ Receive Data Register Full 0 = Wait 1 = Read Transmit Data Register Empty 0 = Wait 1 = Write Transmitter Ready 0 = Data in HI 1 = Data Not in HI Host Flags Read Only DMA Status 0 = DMA Disabled 1 = DMA Enabled Host Request 0 = HREQ Deasserted 1 = HREQ Asserted 7 HREQ 6 DMA 5 4 HF3 3 HF2 2 1 0 RXDF Interrupt Status Register (ISR) $2 Read/Write Reset = $06 * 0 TRDY TXDE Program as * *= Reserved, Registers 0 Figure D-9 Interrupt Control and Interrupt Status MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D D-23 Freescale Semiconductor, Inc. Programming Reference Application: Date: Programmer: Sheet 5 of 6 HOST Freescale Semiconductor, Inc... 7 IV7 6 IV6 5 IV5 4 IV4 3 IV3 2 IV2 1 IV1 0 IV0 Interrupt Vector Register (IVR) Reset = $0F Contains the interrupt vector or number Host Vector Contains Host Command Interrupt Address O 2 Host Command Handshakes Executing Host Command Interrupts 7 HC7 6 HC6 5 HC5 4 HC4 3 HC3 2 HC2 1 HC1 0 HC0 Command Vector Register (CVR) Reset = $2A Contains the host command interrupt address Figure D-10 Interrupt Vector and Command Vector Registers D-24 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Programming Reference Application: Date: Programmer: Sheet 6 of 6 HOST Processor Side Host Receive Data (usually Read by program) Freescale Semiconductor, Inc... 7 Receive Low Byte 07 Receive Middle Byte 07 Receive High Byte 07 Not Used 0 0 0 0 0 0 0 0 0 $7 Receive Byte Registers $7, $6, $5, $4 Read Only Reset = $00 $6 $5 $4 Receive Byte Registers Host Transmit Data (usually loaded by program) 7 Transmit Low Byte 07 Transmit Middle Byte 07 Transmit High Byte 07 Not Used 0 0 0 0 0 0 0 0 0 $7 Transmit Byte Registers $7, $6, $5, $4 Write Only Reset = $00 $6 $5 $4 Figure D-11 Host Receive and Host Transmit Data Registers MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D D-25 Freescale Semiconductor, Inc... D-26 Application: ESSI Control Register A (CRAx) ESSI0 :$FFFFB5 Read/Write ESSI1 :$FFFFA5 Read/Write Reset = $000000 Alignment Control 0 = 16-bit data left aligned to bit 23 1 = 16-bit data left aligned to bit 15 Frame Rate Divider Control DC4:0 = $00-$1F (1 to 32) Divide ratio for Normal mode # of time slots for Network Prescaler Range 0 = O8 1 = O1 PSR = 1 & PM[7:0] = $00 is Prescale Modulus Select PM7:0 = $00-$FF (O1 to O256) Programming Reference ESSI Word Length Control WL2 WL1 WL0 Number of bits/word 0 0 08 0 0 1 12 0 1 0 16 0 1 1 24 1 0 0 32 (data in first 24 bits) 1 0 1 32 (data in last 24 bits) 1 1 0 Reserved 1 1 1 Reserved Figure D-12 ESSI Control Register A (CRA) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 DSP56309UM/D Select SC1 as Tx#0 drive enable 0 = SC1 functions as serial I/O flag 1 = functions as driver enable of Tx#0 external buffer 1 0 Date: Programmer: * 0 SSC1 WL2 WL1 WL0 ALC DC4 DC3 DC2 DC1 DC0 * 0 PSR *** 000 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0 MOTOROLA * = Reserved, Program as 0 Sheet 1 of 4 Freescale Semiconductor, Inc... Application: ESSI Frame Sync Relative Timing (WL Frame Sync only) 0 = with 1st data bit 1 = 1 clock cycle earlier than 1st data bit 1 = low level (negative) 0 0 1 1 Output Flag x If SYN = 1 and SCD1 = 1 OFx (R) SCx Pin 0 1 0 1 FSL1 FSL0 MOTOROLA Frame Sync Length TX RX Word Word Bit Word Bit Bit Word Bit Serial Control Direction Bits SCDx = 0 (Output) SCDx = 1(Output) SC0 Pin Rx Clk Flag 0 SC1 Pin Rx Frame Sync Flag 1 SC2 Pin Tx Frame Sync Tx, Rx Frame Sync Shift Direction 0 = MSB First 1 = LSB First Clock Source Direction 0 = External Clock 1 = Internal Clock Frame Sync Polarity 0 = high level (positive) Clock Polarity (clk edge data & Frame Sync clocked out/in) 0 = out on rising / in on falling 1 = in on rising / out on falling Sync/Async Control (Tx & Rx transfer together or not) 0 = Asynchronous 1 = Synchronous Mode Select 0 = Normal 1 = Network Transmit 2 Enable (SYN=1 only) 0 = Disable 1 = Enable Transmit 1 Enable (SYN=1 only) 0 = Disable 1 = Enable Transmit 0 Enable 0 = Disable 1 = Enable Receiver Enable 0 = Disable 1 = Enable Transmit Interrupt Enable 0 = Disable 1 = Enable Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 REIE TEIE RLIE TLIE RIE TIE RE TE0 TE1 Figure D-13 ESSI Control Register B (CRB) DSP56309UM/D 8 Receive Interrupt Enable 0 = Disable 1 = Enable Transmit Last Slot Interrupt Enable 0 = Disable 1 = Enable Receive Last Slot Interrupt Enable 0 = Disable 1 = Enable Date: Transmit Exception Interrupt Enable 0 = Disable 1 = Enable Programmer: Receive Exception Interrupt Enable 0 = Disable 1 = Enable 7 6 5 4 3 2 1 0 TE2 MOD SYN CKP FSP FSR FSL1 FSL0 SHFD SCKD SCD2 SCD1 SCD0 OF1 OF0 Sheet 2 of 4 Programming Reference ESSI Control Register B (CRBx) ESSI0 :$FFFFB6 Read/Write ESSI1 :$FFFFA6 Read/Write Reset = $000000 D-27 Freescale Semiconductor, Inc. Programming Reference Application: Date: Programmer: Sheet 3 of 4 ESSI Serial Input Flag 0 If SCD0 = 0, SYN = 1, & TE1 = 0 latch SC0 on FS Serial Input Flag 1 If SCD1 = 0, SYN = 1, & TE2 = 0 latch SC0 on FS Transmit Frame Sync 0 = Sync Inactive 1 = Sync Active Receive Frame Sync 0 = Wait 1 = Frame Sync Occurred Transmitter Underrun Error Flag 0 = OK 1 = Error Receiver Overrun Error Flag 0 = OK 1 = Error Transmit Data Register Empty 0 = Wait 1 = Write Receive Data Register Full 0 = Wait 1 = Read Freescale Semiconductor, Inc... 23 SSI Status Register (SSISRx) ESSI0: $FFFFB7 (Read) ESSI1: $FFFFA7 (Read) 7 RDF 6 5 4 TUE 3 RFS 2 TFS 1 IF1 0 IF0 * 0 TDE ROE SSI Status Bits *= Reserved, program as 0 Figure D-14 ESSI Status Register (SSISR) D-28 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Programming Reference Application: Date: Programmer: Sheet 4 of 4 ESSI 23 ESSI Transmit Slot Mask A TSMAx ESSI0: $FFFFB4 Read/Write ESSI1: $FFFFA4 Read/Write Reset = $FFFF SSI Transmit Slot Mask 0 = IgnoreTime Slot 1 = Activ Time Slot e 16 15 14 13 12 11 10 9 TS15 TS14 TS13 TS12 TS11 TS10 TS9 8 TS8 7 TS7 6 TS6 5 TS5 4 TS4 3 TS3 2 TS2 1 TS1 0 TS0 ** 00 Freescale Semiconductor, Inc... ESSI Transmit Slot Mask A * = Reserved, Program as 0 SSI Transmit Slot Mask 0 = IgnoreTime Slot 1 = Active Time Slot 23 ESSI Transmit Slot Mask B TSMBx ESSI0: $FFFFB3 Read/Write ESSI1: $FFFFA3 Read/Write Reset = $FFFF 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ** 00 TS31 TS30 TS29 TS28 TS27 TS26 TS25 TS24 TS23 TS22 TS21 TS20 TS19 TS18 TS17 TS16 ESSI Transmit Slot Mask B * = Reserved, Program as 0 SSI Receive Slot Mask 0 = IgnoreTime Slot 1 = Active Time Slot 23 SSI Receive Slot Mask A RSMAx ESSI0: $FFFFB2 Read/Write ESSI1: $FFFFA2 Read/Write Reset = $FFFF 16 15 14 13 12 11 10 9 RS15 RS14 RS13 RS12 RS11 RS10 RS9 8 RS8 7 RS7 6 RS6 5 RS5 4 RS4 3 2 1 RS1 0 RS0 ** 00 RS3 RS2 ESSI Receive Slot Mask A * = Reserved, Program as 0 SSI Receive Slot Mask 0 = Ignore Time Slot 1 = Active Time Slot SSI Receive Slot Mask B RSMBx ESSI0: $FFFFB1 Read/Write ESSI1: $FFFFA1 Read/Write Reset = $FFFF 23 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ** 00 RS31 RS30 RS29 RS28 RS27 RS26 RS25 RS24 RS23 RS22 RS21 RS20 RS19 RS18 RS17 RS16 ESSI Receive Slot Mask B * = Reserved, Program as 0 Figure D-15 ESSR Transmit and Receive Slot Mask Registers (TSM, RSM) MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D D-29 Freescale Semiconductor, Inc. Programming Reference Application: Date: Programmer: Sheet 1 of 3 SCI Transmitter Enable 0 = Transmitter Disable 1 = Transmitter Enable Word Select Bits 0 0 0 = 8-bit Synchronous Data (Shift Register Mode) 0 0 1 = Reserved 0 1 0 = 10-bit Asynchronous (1 Start, 8 Data, 1 Stop) 0 1 1 = Reserved 1 0 0 = 11-bit Asynchronous (1 Start, 8 Data, Even Parity, 1 Stop) 1 0 1 = 11-bit Asynchronous (1 Start, 8 Data, Odd Parity, 1 Stop) 1 1 0 = 11-bit Multidrop (1 Start, 8 Data, Data Type, 1 Stop) 1 1 1 = Reserved Receiver Wakeup Enable 0 = receiver has awakened 1 = Wakeup function enabled Wired-Or Mode Select 1 = Multidrop 0 = Point to Point Receiver Enable 0 = Receiver Disabled 1 = Receiver Enabled SCI Shift Direction 0 = LSB First 1 = MSB First Freescale Semiconductor, Inc... Idle Line Interrupt Enable 0 = Idle Line Interrupt Disabled 1 = Idle Line Interrupt Enabled Receive Interrupt Enable 0 = Receive Interrupt Disabled 1 = Idle Line Interrupt Enabled Transmit Interrupt Enable 0 = Transmit Interrupts Disabled 1 = Transmit Interrupts Enabled Timer Interrupt Enable 0 = Timer Interrupts Disabled 1 = Timer Interrupts Enabled SCI Timer Interrupt Rate 0 = O 32, 1 = O 1 SCI Clock Polarity 0 = Clock Polarity is Positive 1 = Clock Polarity is Negative SCI Receive Exception Inerrupt 0 = Receive Interrupt Disable 1 = Receive Interrupt Enable Send Break 0 = Send break, then revert 1 = Continually send breaks Wakeup Mode Select 0 = Idle Line Wakeup 1 = Address Bit Wakeup 23 SCI Control Register (SCR) Address X:$FFFF9C Read/Write 16 15 14 13 12 11 10 9 REIE SCKP STIR TMIE TIE RIE ILIE TE 8 RE 7 6 5 4 3 2 1 0 * 0 WOMS RWU WAKE SBK SSFTD WDS2 WDS1 WDS0 * = Reserved, Program as 0 SCI Control Register (SCR) Figure D-16 SCI Control Register (SCR) D-30 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Programming Reference Application: Date: Programmer: Sheet 2 of 3 SCI Overrun Error Flag 0 = No error 1 = Overrun detected Idle Line Flag 0 = Idle not detected 1 = Idle State Receive Data Register Full 0 = Receive Data Register Empty 1 = Receive Data Register Full Transmitter Data Register Empty 0 = Transmitter Data Register full 1 = Transmitter Data Register empty Transmitter Empty 0 = Transmitter full 1 = Transmitter empty Parity Error Flag 0 = No error 1 = Incorrect Parity detected Framing Error Flag 0 = No error 1 = No Stop Bit detected Received Bit 8 0 = Data 1 = Address Freescale Semiconductor, Inc... 23 SCI Status Register (SSR) Address X:$FFFF93 Read Only Reset = $000003 7 R8 6 FE 5 PE 4 OR 3 2 1 0 * 0 IDLE RDRF TDRE TRNE $0 $3 *= Reserved, Program as 0 SCI Status Register (SSR) Clock Divider Bits CD11 CD0) TCM RCM TX Clock RX Clock SCLK Pin Mode 0 0 Internal Internal Output Synchronous/Asynchronous 0 1 Internal External Input Asynchronous only 1 0 External Internal Input Asynchronous only 1 1 External External Input Synchronous/Asynchronous Transmitter Clock Mode/Source 0 = Internal clock for Transmitter 1 = External clock from SCLK Receiver Clock Mode/Source 0 = Internal clock for Receiver 1 = External clock from SCLK Clock Divider Bits CD11 CD0) CD11 CD0 Icyc Rate $000 Icyc/1 $001 Icyc/2 $002 Icyc/3 $FFE Icyc/4095 $FFF Icyc/4096 Clock Out Divider 0 = Divide clock by 16 before feed to SCLK 1 = Feed clock to directly to SCLK SCI Clock Prescaler 0 = O1 1 = O 8 23 15 14 13 12 11 10 TCM RCM SCP 9 8 CD8 7 CD7 6 CD6 5 CD5 4 CD4 3 CD3 2 CD2 1 CD1 0 CD0 * 0 COD CD11 CD10 CD9 SCI Clock Control Register (SCCR) *= Reserved, Program as 0 Figure D-17 SCI Status and Clock Control Registers (SSR, SCCR) MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D D-31 Freescale Semiconductor, Inc. Programming Reference Application: Date: Programmer: Sheet 3 of 3 SCI X0 23 OAO Unpacking 16 15 STX STX STX OBO 87 OCO 0 SCI Transmit Data Registers Address X:$FFFF95 X:$FFFF97 Write Reset = xxxxxx Note: X:$FFFF97 X:$FFFF96 X:$FFFF95 Freescale Semiconductor, Inc... STX is the same register decoded at four different addresses SCI Transmit SR SCI Transmit Data Registers TXD X:$FFFF94 STXA RXD SCI Receive SR 23 SCI Receive Data Registers Address X:$FFFF98 X:$FFFF9A Read Reset = xxxxxx X:$FFFF9A X:$FFFF99 X:$FFFF98 SRX 16 15 SRX 87 SRX 0 Packing OAO Note: STX is the same register decoded at three different addresses SCI Receive Data Registers OBO OCO Figure D-18 SCI Receive and Transmit Data Registers (SRX, TRX) D-32 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Programming Reference Application: Date: Programmer: Sheet 1 of 3 Timers PS (1:0) 00 01 10 11 Prescaler Clock Source Internal CLK/2 TIO0 TIO1 TIO2 Freescale Semiconductor, Inc... 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 * 0 PS1 PS0 Prescaler Preload Value (PL [0:20]) Timer Prescaler Load Register TPLR:$FFFF83 Read/Write Reset = $000000 *= Reserved, Program as 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 *** 000 Timer Prescaler Count Register TPCR:$FFFF82 Read Only Reset = $000000 Current Value of Prescaler Counter (PC [0:20]) *= Reserved, Program as 0 Figure D-19 Timer Prescaler Load/Count Register (TPLR, TPCR) MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D D-33 Freescale Semiconductor, Inc. Programming Reference Application: Date: Programmer: Sheet 2 of 3 Timers Inverter Bit 8 0 = 0- to-1 transitions on TIO input increment the counter, or high pulse width measured, or high pulse output on TIO 1 = 1-to-0 transitions on TIO input increment the counter, or low pulse width measured, or low pulse output on TIO Timer Reload Mode Bit 9 0 = Timer operates as a free running counter Freescale Semiconductor, Inc... 1 = Timer is reloaded when selected condition occurs Direction Bit 11 0 = TIO pin is input 1 = TIO pin is output Data Input Bit 12 0 = Zero read on TIO pin 1 = One read on TIO pin Data Output Bit 13 0 = Zero written to TIO pin 1 = One written to TIO pin Prescaled Clock Enable Bit 15 0 = Clock source is CLK/2 or TIO 1 = Clock source is prescaler output Timer Compare Flag Bit 21 0 = O1O has been written to TCSR(TCF), or timer compare interrupt serviced 1 = Timer Compare has occurred Timer Overflow Flag Bit 20 0 = O1O has been written to TCSR(TOF), or timer Overflow interrupt serviced 1 = Counter wraparound has occurred TC (3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Timer Control Bits 4 7 (TC0 TC3) TIO Clock Mode GPIO Internal Timer Output Internal Timer Pulse Output Internal Timer Toggle Input External Event Counter Input Internal Input Width Input Internal Input Period Input Internal Capture Output Internal Pulse Width Modulation Reserved Output Internal Watchdog Pulse Output Internal Watchdog Toggle Reserved Reserved Reserved Reserved Reserved Timer Enable Bit 0 0 = Timer Disabled 1 = Timer Enabled Timer Overflow Interrupt Enable Bit 1 0 = Overflow Interrupts Disabled 1 = Overflow Interrupts Enabled Timer Compare Interrupt Enable Bit 2 0 = Compare Interrupts Disabled 1 = Compare Interrupts Enabled 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 TC3 6 TC2 5 TC1 4 TC0 3 2 1 0 TE ** 00 TCF TOF * * ** 0000 PCE * 0 DO DI DIR * 0 TRM INV * 0 TCIE TQIE Timer Control/Status Register TCSR0:$FFFF8F Read/Write TCSR1:$FFFF8B Read/Write TCSR2:$FFFF87 Read/Write Reset = $000000 *= Reserved, Program as 0 Figure D-20 Timer Control/Status Register (TCSR) D-34 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Programming Reference Application: Date: Programmer: Sheet 3 of 3 Timers 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Timer Reload Value 8 7 6 5 4 3 2 1 0 Freescale Semiconductor, Inc... Timer Load Register TLR0:$FFFF8E Write Only TLR1:$FFFF8A Write Only TLR2:$FFFF86 Write Only Reset = $000000 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Value Compared to Counter Value Timer Compare Register TCPR0:$FFFF8D Read/Write TCPR1:$FFFF89 Read/Write TCPR2:$FFFF85 Read/Write Reset = $000000 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Timer Count Value 8 7 6 5 4 3 2 1 0 Timer Count Register TCR0:$FFFF8C Read Only TCR1:$FFFF88 Read Only TCR2:$FFFF84 Read Only Reset = $000000 Figure D-21 Timer Load, Compare, Count Registers (TLR, TCPR, TCR) MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D D-35 Freescale Semiconductor, Inc. Programming Reference Application: Date: Programmer: Sheet 1 of 4 GPIO Port B (HI08) Freescale Semiconductor, Inc... Host Data Direction Register (HDDR) X:$FFFFC8 Write Reset = $0 15 DR15 14 13 12 DR12 11 DR11 10 DR10 9 DR9 8 DR8 7 DR7 6 DR6 5 DR5 4 DR4 3 DR3 2 DR2 1 DR1 0 DR0 DR14 DR13 DRx = 1 (R) HIx is Output DRx = 0 (R) HIx is Input Host Data Register (HDR) X:$FFFFC9 Write Reset = Undefined 15 D15 14 D14 13 D13 12 D12 11 D11 10 D10 9 D9 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 DRx holds value of corresponding HI08 GPIO pin. Function depends on HDDR. Figure D-22 Host Data Direction and Host Data Registers (HDDR, HDR) D-36 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Programming Reference Application: Date: Programmer: Sheet 2 of 4 GPIO Port C Control Register (PCRC) X:$FFFFBF ReadWrite Reset = $0 Port C (ESSI0) 23 6 5 PC5 4 PC4 3 PC3 2 PC2 1 PC1 0 PC0 Freescale Semiconductor, Inc... ** 00 PCn = 1 (R) Port Pin configured as ESSI PCn = 0 (R) Port Pin configured as GPIO Port C Direction Register (PRRC) X:$FFFFBE ReadWrite Reset = $0 23 6 5 PDC5 4 PDC4 3 PDC3 2 PDC2 1 PDC1 0 PDC0 ** 00 PDCn = 1 (R) Port Pin is Output PDCn = 0 (R) Port Pin is Input Port C GPIO Data Register (PDRC) X:$FFFFBD ReadWrite Reset = $0 23 6 5 PD5 4 PD4 3 PD3 2 PD2 1 PD1 0 PD0 ** 00 port pin n is GPIO input, then PDn reflects the value on port pin n if port pin n is GPIO output, then value written to PDn is reflected on port pin n *= Reserved, Program as 0 Figure D-23 Port C Registers (PCRC, PRRC, PDRC) MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D D-37 Freescale Semiconductor, Inc. Programming Reference Application: Date: Programmer: Sheet 3 of 4 GPIO Port D Control Register (PCRD) X:$FFFFAF ReadWrite Reset = $0 Port D (ESSI1) 23 6 5 PC5 4 PC4 3 PC3 2 PC2 1 PC1 0 PC0 Freescale Semiconductor, Inc... ** 00 PCn = 1 (R) Port Pin configured as ESSI PCn = 0 (R) Port Pin configured as GPIO Port D Direction Register (PRRD) X:$FFFFAE ReadWrite Reset = $0 23 6 5 PDC5 4 PDC4 3 PDC3 2 PDC2 1 PDC1 0 PDC0 ** 00 PDCn = 1 (R) Port Pin is Output PDCn = 0 (R) Port Pin is Input Port D GPIO Data Register (PDRD) X:$FFFFAD ReadWrite Reset = $0 23 6 5 PD5 4 PD4 3 PD3 2 PD2 1 PD1 0 PD0 ** 00 port pin n is GPIO input, then PDn reflects the value on port pin n if port pin n is GPIO output, then value written to PDn is reflected on port pin n *= Reserved, Program as 0 Figure D-24 Port D Registers (PCRD, PRRD, PDRD) D-38 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. Programming Reference Application: Date: Programmer: Sheet 4 of 4 GPIO Port E Control Register (PCRE) X:$FFFF9F ReadWrite Reset = $0 Port E (SCI) 23 6 5 4 3 2 PC2 1 PC1 0 PC0 Freescale Semiconductor, Inc... ***** 00000 PCn = 1 (R) Port Pin configured as SCI PCn = 0 (R) Port Pin configured as GPIO Port E Direction Register (PRRE) X:$FFFF9E ReadWrite Reset = $0 23 6 5 4 3 2 PDC2 1 PDC1 0 PDC0 ***** 00000 PDCn = 1 (R) Port Pin is Output PDCn = 0 (R) Port Pin is Input Port E GPIO Data Register (PDRE) X:$FFFF9D ReadWrite Reset = $0 23 6 5 4 3 2 PD2 1 PD1 0 PD0 ***** 00000 port pin n is GPIO input, then PDn reflects the value on port pin n if port pin n is GPIO output, then value written to PDn is reflected on port pin n *= Reserved, Program as 0 Figure D-25 Port E Registers (PCRE, PRRE, PDRE) MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D D-39 Freescale Semiconductor, Inc. Programming Reference Freescale Semiconductor, Inc... D-40 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. INDEX A A0A17 signals 2-9 AA0AA3 signals 2-10 adder modulo 1-9 offset 1-9 reverse-carry 1-9 address attribute signals 2-10 address bus 2-3 signals 2-9 Address Generation Unit 1-9 addressing modes 1-10 AGU 1-9 ALC bit 7-13 Alignment Control bit (ALC) 7-13 applications 1-7 Asynchronous/Synchronous bit (SYN) 7-18 Breakpoint 1 Read/Write Select bits (RW10RW11) 10-13 BSDL listing PBGA C-8 TQFP C-2 BSR register 11-7 BT0BT1 bits 10-14 bus address 2-4 data 2-4 external address 2-9 external data 2-9 multiplexed 2-4 non-multiplexed 2-4 bus busy signal (BB) 2-13 bus clock not signal (BCLK) 2-13 bus clock signal (BCLK) 2-13 bus control 2-3 bus grant signal (BG) 2-12 bus parking 2-13 bus request signal (BR) 2-12 buses internal 1-13 BYPASS instruction 11-11 Freescale Semiconductor, Inc... B BA3BA10 bits 6-12 barrel shifter 1-8 Base Address bits (BA3BA10) 6-12 BB signal 2-13 BCLK signal 2-13 BCLK signal 2-13 BG signal 2-12 bootstrap 4-4 bootstrap from byte-wide external memory 4-7 bootstrap program options invoking 4-5 bootstrap ROM 3-7 bootstrap through HI08 (68302/68360) 4-9 bootstrap through HI08 (ISA) 4-8 bootstrap through HI08 (Multiplexed) 4-9 bootstrap through HI08 (non-multiplexed) 4-8 bootstrap through SCI 4-7 Boundary Scan Description Language PBGA C-8 TQFP C-2 Boundary Scan Register (BSR) 11-7 BR signal 2-12 break 8-9 Breakpoint 0 and 1 Event bits (BT0BT1) 10-14 Breakpoint 0 Condition Code Select bits (CC00CC01) 10-13 Breakpoint 0 Read/Write Select bits (RW00RW01) 10-12 Breakpoint 1 Condition Code Select bits (CC10CC11) 10-14 C CAS signal 2-13 CC00CC01 bits 10-13 CC10CC11 bits 10-14 CD0CD11 bits 8-16 Central Processing Unit (CPU) 1-3 CKP bit 7-18 CLAMP instruction 11-10 CLKGEN 1-11 CLKOUT signal 2-8 clock 1-7, 2-3 Clock Divider bits (CD0CD11) 8-16 Clock Generator (CLKGEN) 1-11 Clock Out Divider bit (COD) 8-16 clock output signal (CLKOUT) 2-8 Clock Polarity bit (CKP) 7-18 clock signals 2-7 Clock Source Direction bit (SCKD) 7-16 CMOS 1-7 COD bit 8-16 code compatible 1-7 column address strobe signal (CAS) 2-13 CRA register 7-11 MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D I-1 Freescale Semiconductor, Inc. D bits 07NPrescale Modulus Select bits (PM0PM7) 7-11 bits 810Nreserved bits 7-11 bit 11NPrescaler Range bit (PSR) 7-11 bits 1216NFrame Rate Divider Control bits (DC4DC0) 7-12 bit 17Nreserved bit 7-13 bit 18NAlignment Control bit (ALC) 7-13 bits 1921NWord Length Control bits (WL0WL1) 7-14 bit 22NSelect SC1 as Transmitter 0 Drive Enable bit (SSC1) 7-14 bit 23Nreserved bit 7-14 reserved bitsNbit 17 7-13 reserved bitsNbit 23 7-14 reserved bitsNbits 810 7-11 CRB register bits 01NSerial Output Flag bits (OF0OF1) 7-15 bit 2NSerial Control 0 Direction bit (SCD0) 7-16 bit 3NSerial Control 1 Direction bit (SCD1) 7-16 bit 4NSerial Control 2 Direction bit (SCD2) 7-16 bit 5NClock Source Direction bit (SCKD) 7-16 bit 6NShift Direction bit (SHFD) 7-17 bits 78NFrame Sync Length bits (FSL1FSL0) 7-17 bit 9NFrame Sync Relative Timing bit (FSR) 7-17 bit 10NFrame Sync Polarity bit (FSP) 7-17 bit 11NClock Polarity bit (CKP) 7-18 bit 12NAsynchronous/Synchronous bit (SYN) 7-18 bit 13NESSI Mode Select bit (MOD) 7-20 bit 14NESSI Transmit 2 Enable bit (TE2) 7-22 bit 15NESSI Transmit 1 Enable bit (TE1) 7-23 bit 16NESSI Transmit 0 Enable bit (TE0) 7-24 bit 17NESSI Receive Enable bit (RE) 7-26 bit 18NESSI Transmit Interrupt Enable bit (TIE) 7-26 bit 19NESSI Receive Interrupt Enable bit (RIE) 7-26 bit 20NESSI Transmit Last Slot Interrupt Enable bit (TLIE) 7-26 bit 21NESSI Receive Last Slot Interrupt Enable bit (RLIE) 7-27 bit 22NESSI Transmit Exception Interrupt Enable bit (TEIE) 7-27 bit 23NESSI Receive Exception Interrupt Enable bit (REIE) 7-27 crystal input 2-8 CVR register bits 06NHost Vector bits (HV0HV6) 6-25 D D0D23 2-10 data ALU 1-8 registers 1-8 data bus 2-3 signals 2-10 Data Output bit (DO) 9-14 DC4DC0 bits 7-12 DE signal 2-37, 10-4 Debug Event signal (DE signal) 10-4 Debug mode in OnCE module 10-16 DEBUG_REQUEST instruction 11-11 executing during Stop state 10-17 executing during Wait state 10-17 executing in OnCE module 10-17 Direct Memory Access (DMA) 1-15 Divide Factor (DF) 1-11 DMA 1-15 triggered by timer 9-27 DO bit 9-14 DO loop 1-10 Double Data Strobe 2-4 Double Host Request bit (HDRQ) 6-23 DRAM 1-13 DS 2-4 DSP56300 core 1-3, 1-6 DSP56300 Family Manual 1-3, 1-7 DSP56303 Functional Signal Groupings 2-3 signal groupings 2-3 DSP56303 Technical Data 1-3 Freescale Semiconductor, Inc... E ENABLE_ONCE instruction 11-11 Enhanced Synchronous Serial Interface (ESSI) 1-16, 2-3, 2-25, 2-28 Enhanced Synchronous Serial Interface 0 2-24 Enhanced Synchronous Serial Interface 1 2-28 equates BIU B-13 I-2 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. F bus interface unit B-13 direct memory access B-10 DMA B-10 enhanced serial communication interface B-5 ESSI B-5 exception processing B-7 HI08 B-3 host interface B-3 i/o port programming B-3 interrupt B-15 phase locked loop B-12 PLL B-12 SCI B-4 serial communication interface B-4 timer module B-9 ESSI 2-4 after reset 7-36 asynchronous operating mode 7-40 frame sync length 7-41 frame sync polarity 7-42 frame sync selection 7-41 frame sync word length 7-41 GPIO functionality 7-43 initialization 7-36 interrupts 7-37 Network mode 7-40 Normal mode 7-40 operating mode 7-36 operating modes 7-40 Port Control Register (PCR) 7-43 Port Data Register (PDR) 7-45 Port Direction Register (PRR) 7-44 programming model 7-8 synchronous operating mode 7-40 ESSI Control Register A (CRA) 7-11 ESSI Mode Select bit (MOD) 7-20 ESSI Receive Data Register (RX) 7-33 ESSI Receive Enable bit (RE) 7-26 ESSI Receive Exception Interrupt Enable bit (REIE) 7-27 ESSI Receive Interrupt Enable bit (RIE) 7-26 ESSI Receive Last Slot Interrupt Enable bit (RLIE) 7-27 ESSI Receive Shift Register 7-33 ESSI Receive Slot Mask Registers (RSMA, RSMB) 7-35 ESSI Status Register (SSISR) 7-27 ESSI Time Slot Register (TSR) 7-34 ESSI Transmit 0 Enable bit (TE0) 7-24 ESSI Transmit 1 Enable bit (TE1) 7-23 ESSI Transmit 2 Enable bit (TE2) 7-22 Freescale Semiconductor, Inc... ESSI Transmit Data registers (TX2, TX1, TX0) 7-34 ESSI Transmit Exception Interrupt Enable bit (TEIE) 7-27 ESSI Transmit Interrupt Enable bit (TIE) 7-26 ESSI Transmit Last Slot Interrupt Enable bit (TLIE) 7-26 ESSI Transmit Shift Registers 7-33 ESSI Transmit Slot Mask Registers (TSMA, TSMB) 7-34 ESSI0 2-24 ESSI0 (GPIO) 5-3 ESSI1 2-28 ESSI1 (GPIO) 5-4 EX bit 10-5 exception processing equates B-7 Exit Command bit (EX) 10-5 expanded mode 4-6 EXTAL 2-7 EXTAL signal 2-7 external address bus 2-9 external bus control 2-9, 2-11, 2-12 external clock/crystal input 2-7 external data bus 2-9 external interrupt request A signal 2-14 external interrupt request B signal 2-15 external interrupt request C signal 2-15 external interrupt request D signal 2-16 external memory expansion port 2-9 EXTEST instruction 11-8 F FE bit 8-15 Frame Rate Divider Control bits (DC4DC0) 7-12 Frame Sync Length bits (FSL1FSL0) 7-17 Frame Sync Polarity bit (FSP) 7-17 Frame Sync Relative Timing bit (FSR) 7-17 frame sync selection ESSI 7-41 Framing Error Flag bit (FE) 8-15 frequency operation 1-7 FSL1FSL0 bits 7-17 FSP bit 7-17 FSR bit 7-17 functional groups 2-4 G general purpose input/output (GPIO) 2-34 Global Data Bus 1-13 MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D I-3 Freescale Semiconductor, Inc. H GO Command bit (GO) 10-6 GPIO 1-15, 2-4, 2-34 on HI08 6-30 Timers 2-4 GPIO (ESSI0, Port C) 5-3 GPIO (ESSI1, Port D) 5-4 GPIO (HI08, Port B) 5-3 GPIO (SCI, Port E) 5-4 GPIO (Timer) 5-4 GPIO functionality on ESSI 7-43 ground 2-3, 2-6 address bus 2-6 bus control 2-7 data bus 2-7 ESSI 2-7 host interface 2-7 PLL 2-6 quiet 2-6 SCI 2-7 timer 2-7 bit 2NHost Command Interrupt Enable bit (HCIE) 6-10 bits 3, 4NHost Flag 2 and 3 bits (HF2, HF3) 6-10 reserved bitsNbits 515 6-10 HCS signal 2-21 HCSEN bit 6-13 HCSP bit 6-16 HDDR register 6-17 HDDS bit 6-15 HDR register 6-17 HDRQ bit 6-23 HDS signal 2-20 HDSP bit 6-14 HEN bit 6-14 HF0 bit 6-24 HF0, HF1 bits 6-11 HF1 bit 6-24 HF2 bit 6-27 HF2, HF3 bits 6-10 HF3 bit 6-27 HGEN bit 6-13 HI08 1-16, 2-3, 2-4, 2-16, 2-18, 2-19, 2-21, 6-3 (GPIO) 5-3 data transfer 6-31 DSP side control registers 6-8 DSP side data registers 6-8 DSP side registers after reset 6-18 DSP to host data word 6-5 handshaking protocols 6-5 interrupts 6-5 mapping 6-4 transfer modes 6-5 external host programmerOs model 6-20 GPIO 6-30 HI08 to DSP core interface 6-3 HI08 to host processor interface 6-4 Host Base Address Register (HBAR) 6-12 Host Control Register (HCR) 6-9, 6-10 Host Data Direction Register (HDDR) 6-17 Host Data Register (HDR) 6-17 Host Port Control Register (HPCR) 6-12 Host Receive Data Register (HRX) 6-8 host side Interface Control Register (ICR) 6-22 Interface Status Register (ISR) 6-26 Interface Vector Register (IVR) 6-28 Freescale Semiconductor, Inc... H H0H7 signals 2-18 HA0 signal 2-18 HA1 signal 2-19 HA2 signal 2-19 HA8 signal 2-19 HA10 signal 2-21 HA9 signal 2-19 HA8EN bit 6-13 HA9EN bit 6-13 HAD0HAD7 signals 2-18 HAEN bit 6-14 HAP bit 6-16 hardware stack 1-10 HAS/HAS 2-18 HASP bit 6-15 HBAR register 6-12 bits 07NBase Address bits (BA3BA10) 6-12 reserved bitsNbits 515 6-12 HCIE bit 6-10 HCP bit 6-11 HCR register 6-9, 6-10 bit 0NHost Receive Interrupt Enable bit (HRIE) 6-10 bit 1NHost Transmit Interrupt Enable bit (HTIE) 6-10 I-4 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. H Receive Byte Registers (RXH, RXM, RXL) 6-28 Transmit Byte Registers (TXH, TXM, TXL) 6-29 host side registers after reset 6-30 Host Status Register (HSR) 6-11 host to DSP data word 6-3 handshaking protocols 6-4 instructions 6-4 mapping 6-3 transfer modes 6-3 Host Transmit Data Register (HTX) 6-9 polling 6-31 registers 6-7 servicing interrupts 6-32 HI-Z instruction 11-10 HLEND bit 6-24 HMUX bit 6-15 Host Acknowledge Enable bit (HAEN) 6-14 Host Acknowledge Polarity bit (HAP) 6-16 host acknowledge signal (HACK/HACK 2-23 host address 10 signal (HA10) 2-21 host address 8 signal (HA8) 2-19 host address 9 signal (HA9) 2-19 host address input 0 signal (HA0) 2-18 host address input 1 signal (HA1) 2-19 host address input 2 signal (HA2) 2-19 Host Address Line 8 Enable bit (HA8EN) 6-13 Host Address Line 9 Enable bit (HA9EN) 6-13 host address signal HAD0HAD7) 2-18 Host Address Strobe Polarity bit (HASP) 6-15 host address strobe signal (HAS/HAS) signal 2-18 Host Base Address Register (HBAR) 6-12 Host Chip Select Enable bit (HCSEN) 6-13 Host Chip Select Polarity bit (HCSP) 6-16 host chip select signal (HCS) 2-21 Host Command Interrupt Enable bit (HCIE) 6-10 Host Command Pending bit (HCP) 6-11 Host Control Register (HCR) 6-9, 6-10 Host Data Direction Register (HDDR) 6-17 Host Data Register (HDR) 6-17 host data signal (H0H7) 2-18 Host Data Strobe Polarity bit (HDSP) 6-14 host data strobe signal (HDS/HDS) 2-20 Host Dual Data Strobe bit (HDDS) 6-15 Host Enable bit (HEN) 6-14 Host Flag 0 and 1 bits (HF0, HF1) 6-11 Host Flag 0 bit (HF0) 6-24 Host Flag 1 bit (HF1) 6-24 Host Flag 2 and 3 bits (HF2, HF3) 6-10 Host Flag 2 bit (HF2) 6-27 Host Flag 3 bit (HF3) 6-27 Host GPIO Port Enable bit (HGEN) 6-13 Host Interface 1-16, 2-3, 2-4, 2-16, 2-18, 2-19, 2-21, 6-3 Host Little Endian bit (HLEND) 6-24 Host Multiplexed Bus bit (HMUX) 6-15 host port configuration 2-17 usage considerations 2-16 Host Port Control Register (HPCR) 6-12 host read data signal (HRD/HRD) signal 2-20 host read/write signal (HRW) 2-20 Host Receive Data Full bit (HRDF) 6-11 Host Receive Data Register (HRX) 6-8 Host Receive Interrupt Enable bit (HRIE) 6-10 Host Request Double 2-4 Single 2-4 Host Request Enable bit (HREN) 6-14 Host Request Open Drain bit (HROD) 6-14 Host Request Polarity bit (HRP) 6-16 host request signal (HREQ/HREQ 2-22 Host Status Register (HSR) 6-11 Host Transmit Data Empty bit (HTDE) 6-11 Host Transmit Data Register (HTX) 6-9 Host Transmit Interrupt Enable bit (HTIE) 6-10 Host Vector bits (HV0HV6) 6-25 host write data signal (HWR/HWR) 2-20 HPCR register 6-12 bit 0NHost GPIO Port Enable bit (HGEN) 6-13 bit 1NHost Address Line 8 bit (HA8EN) 6-13 bit 2NHost Address Line 9 bit (HA9EN) 6-13 bit 3NHost Chip Select Enable bit (HCSEN) 6-13 bit 4NHost Request Enable bit (HREN) 6-14 bit 5NHost Acknowledge Enable bit (HAEN) 6-14 bit 6NHost Enable bit (HEN) 6-14 bit 7Nreserved bit 6-14 bit 8NHost Request Open Drain bit (HROD) 6-14 bit 9NHost Data Strobe Polarity bit (HDSP) 6-14 bit 10NHost Address Strobe Polarity bit (HASP) 6-15 bit 11NHost Multiplexed Bus bit (HMUX) 6-15 bit 12NHost Dual Data Strobe bit (HDDS) 6-15 bit 13NHost Chip Select Polarity bit (HCSP) 6-16 bit 14NHost Request Polarity bit (HRP) 6-16 Freescale Semiconductor, Inc... MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D I-5 Freescale Semiconductor, Inc. I bit 15NHost Acknowledge Polarity bit (HAP) 6-16 reserved bitNbit 7 6-14 HR 2-4 HRD/HRD 2-20 HRDF bit 6-11 HREN bit 6-14 HRIE bit 6-10 HROD bit 6-14 HRP bit 6-16 HRRQ/HRRQ 2-23 HRW 2-20 HRX register 6-8 HSR register 6-11 bit 0NHost Receive Data Full bit (HRDF) 6-11 bit 1NHost Transmit Data Empty bit (HTDE) 6-11 bit 2NHost Command Pending bit (HCP) 6-11 bits 3, 4NHost Flag 0 and 1 bits (HF0, HF1) 6-11 reserved bitsNbits 515 6-11 HTDE bit 6-11 HTIE bit 6-10 HTRQ/HTRQ 2-22 HTX register 6-9 HV0HV6 bits 6-25 HWR/HWR signal 2-20 location 3-8 instruction set 1-7 Interface Control Register (ICR) 6-22 Interface Status Register (ISR) 6-26 Interface Vector Register (IVR) 6-28 internal buses 1-13 interrupt 1-10 ESSI 7-37 priority levels 4-12 servicing on HI08 6-32 sources 4-9 interrupt and mode control 2-3, 2-14, 2-15 interrupt control 2-14, 2-15 interrupt equates B-15 Interrupt Mode Enable bit (IME) 10-8 Interrupt Priority Register P (IPRNP) 4-13 interrupts DMA equates B-15 ending address B-16 ESSI equates B-16 host equates B-16 non-maskable B-15 request pins B-15 SCI equates B-16 timer equates B-15 INV bit 9-11 Inverter bit (INV) 9-11 IPRNP 4-13 ISR register 6-26 bit 0NReceive Data Register Full bit (RXDF) 6-26 bit 1NTransmit Data Register Empty bit (TXDE) 6-27 bit 2NTransmitter Ready bit (TRDY) 6-27 bit 3NHost Flag 2 bit (HF2) 6-27 bit 4NHost Flag 3 bit (HF3) 6-27 bit 5Nreserved bit 6-27 bit 6Nreserved bit 6-27 reserved bitsNbits 5,6 6-27 IVR register 6-28 Freescale Semiconductor, Inc... I ICR register 6-22 bit 0NReceive Request Enable bit (RREQ) 6-23 bit 1NTransmit Request Enable bit (TREQ) 6-23 bit 2NDouble Host Request bit (HDRQ) 6-23 bit 3NHost Flag 0 bit (HF0) 6-24 bit 4NHost Flag 1 bit (HF1) 6-24 bit 5NHost Little Endian bit (HLEND) 6-24 bit 6Nreserved bit 6-24 reserved bitNbit 6 6-24 IDCODE instruction 11-9 IDLE bit 8-14 Idle Line Flag bit (IDLE) 8-14 Idle Line Interrupt Enable bit (ILIE) 8-11 IF0 bit 7-28 IF1 bit 7-28 ILIE bit 8-11 IME bit 10-8 instruction cache 3-3 J Joint Test Action Group (JTAG) 11-3 JTAG 1-11, 2-35 JTAG instructions BYPASS instruction 11-11 CLAMP instruction 11-10 DEBUG_REQUEST instruction 11-11 I-6 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. K ENABLE_ONCE instruction 11-11 EXTEST instruction 11-8 HI-Z instruction 11-10 IDCODE instruction 11-9 SAMPLE/PRELOAD instruction 11-9 JTAG/OnCE Interface signals Debug Event signal (DE signal) 10-4 K keeper, weak 2-24, 2-25, 2-26, 2-27, 2-28, 2-29, 2-30, 2-31, 2-32, 2-33, 2-34, 2-35 mode select A signal 2-14 mode select B signal 2-15 mode select C signal 2-15 mode select D signal 2-16 modulo adder 1-9 multiplexed bus 2-4 Multiplication Factor bits (MF) 4-18 multiplier-accumulator (MAC) 1-8, 1-9 N non-maskable interrupt 2-8, 2-9 non-multiplexed bus 2-4 Freescale Semiconductor, Inc... L LA register 1-10 LC register 1-10 logic 1-7 Loop Address register (LA) 1-10 Loop Counter register (LC) 1-10 O OBCR register 10-12 bits 01NMemory Breakpoint Select bits (MBS0MBS1) 10-12 bits 23NBreakpoint 0 Read/Write Select bits (RW00RW01) 10-12 bits 45NBreakpoint 0 Condition Code Select bits (CC00CC01) 10-13 bits 67NBreakpoint 1 Read/Write Select bits (RW10RW11) 10-13 bits 89NBreakpoint 1 Condition Code Select bits (CC10CC11) 10-14 bits 1011NBreakpoint 0 and 1 Event Select bits (BT0BT1) 10-14 reserved bitsNbits 1215 10-15 OCR register bits 04NRegister Select bits (RS0RS4) 10-5 bit 5NExit Command bit (EX) 10-5 bit 6NGO Command bit (GO) 10-6 bit 7NRead/Write Command bit (R/W) 10-6 ODEC 10-8 OF0OF1 bits 7-15 offset adder 1-9 OGDBR register 10-20 OMAC0 comparator 10-11 OMAC1 comparator 10-11 OMAL register 10-11 OMBC counter 10-14 OMLR0 register 10-11 OMLR1 register 10-11 OMR register 1-11 OnCE 1-4 commands 10-23 controller 10-4 trace logic 10-15 OnCE Breakpoint Control Register (OBCR) 10-12 M MAC 1-9 Manual Conventions 1-5 MBO bit 10-8 MBS0MBS1 bits 10-12 memory bootstrap ROM 3-7 enabling breakpoints 10-18 external expansion port 1-13 maps 3-9 on-chip 1-12 program RAM 3-6 X data RAM 3-6 Y data RAM 3-7 Memory Breakpoint Occurrence bit (MBO) 10-8 Memory Breakpoint Select bits (MBS0MBS1) 10-12 memory configuration 3-7 memory spaces 3-7 RAM 3-8 MF bits 4-18 MIPS 1-7 MOD bit 7-20 MODA/IRQA 2-14 MODB/IRQB 2-15 MODC/IRQC 2-15 MODD/IRQD 2-16 mode control 2-14, 2-15 Mode Select bit (MOD) 7-20 MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D I-7 Freescale Semiconductor, Inc. P OnCE Command Register (OCR) 10-5 OnCE Decoder (ODEC) 10-8 OnCE GDB Register (OGDBR) 10-20 OnCE Memory Address Comparator 0 (OMAC0) 10-11 OnCE Memory Address Comparator 1 (OMAC1) 10-11 OnCE Memory Address Latch register (OMAL) 10-11 OnCE Memory Breakpoint Counter (OMBC) 10-14 OnCE Memory Limit Register 0 (OMLR0) 10-11 OnCE Memory Limit Register 1 (OMLR1) 10-11 OnCE module 1-12, 10-3 checking for Debug mode 10-24 displaying a specified register 10-26 displaying X data memory 10-26 interaction with JTAG port 10-29 polling the JTAG Instruction Shift register 10-24 reading the Trace buffer 10-25 returning to Normal mode 10-28 saving pipeline information 10-25 OnCE PAB Register for Decode Register (OPABDR) 10-20 OnCE PAB Register for Execute (OPABEX) 10-20 OnCE PAB Register for Fetch Register (OPABFR) 10-20 OnCE PIL Register (OPILR) 10-19 OnCE Program Data Bus Register (OPDBR) 10-19 OnCE Status and Control Register (OSCR) 10-8 OnCE Trace Counter (OTC) 10-16 OnCE/JTAG 2-4 debug event signal (DE) 2-37 test clock signal (TCK) 2-35 test data input signal (TDI) 2-35 test data output signal (TDO) 2-36 test mode select signal (TMS) 2-36 OnCE/JTAG port 2-3 On-Chip Emulation (OnCE) module 1-12 On-Chip Emulation module 10-3 on-chip memory 1-12 program 3-6 X data RAM 3-6 Y data RAM 3-7 OPABDR register 10-20 OPABEX register 10-20 OPABFR register 10-20 OPDBR register 10-19 Operating 4-3 operating mode 4-3 bootstrap from byte-wide external memory 4-7 bootstrap thorugh HI08 (68302/68360) 4-9 bootstrap through HI08 (ISA) 4-8 bootstrap through HI08 (multiplexed) 4-9 bootstrap through HI08 (non-multiplexed) 4-8 bootstrap through SCI 4-7 ESSI 7-36, 7-40 expanded 4-6 expanded mode 4-6 Operating Mode Register (OMR) 1-11 operating modes 4-3 OPILR register 10-19 OR bit 8-14 OSCR register 10-8 bit 0NTrace Mode Enable bit (TME) 10-8 bit 1NInterrupt Mode Enable bit (IME) 10-8 bit 2NSoftware Debug Occurrence bit (SWO) 10-8 bit 3NMemory Breakpoint Occurrence bit (MBO) 10-8 bit 4NTrace Occurrence bit (TO) 10-9 bit 5Nreserved bit 10-9 reserved bitsNbits 823 10-9 OTC counter 10-16 Overrun Error Flag bit (OR) 8-14 Freescale Semiconductor, Inc... P PAB 1-13 PAG 1-10 Parity Error bit (PE) 8-14 PB0PB7 signals 2-18 PB10 signal 2-19 PB11 signal 2-20 PB12 signal 2-20 PB13 signal 2-21 PB14 signal 2-22 PB15 signal 2-23 PB8 signal 2-18 PB9 signal 2-19 PC register 1-10 PC0 signal 2-24 PC0-PC20 bits 9-9 PC1 signal 2-25 PC2 signal 2-25 PC3 signal 2-26 PC4 signal 2-26 PC5 signal 2-27 I-8 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. P PCAP signal 2-8 PCRC register 7-43 PCRD register 7-43 PCRE register 8-27 PCTL register bits 011NMultiplication Factor bits (MF0MF11) 4-18 bit 16NXTAL Disable bit (XTLD) 4-18 bits 2023NPreDivider Factor bits (PD0PD3) 4-18 PCU 1-10 PD bits 4-18 PD0 signal 2-28 PD1 signal 2-28 PD2 signal 2-29 PD3 signal 2-30 PD4 signal 2-30 PD5 signal 2-31 PDB 1-13 PDC 1-10 PDRC register 7-45 PDRD register 7-45 PDRE register 8-28 PE bit 8-14 PE0 signal 2-32 PE1 signal 2-32 PE2 signal 2-33 Peripheral I/O Expansion Bus 1-13 PIC 1-10 PINIT/NMI 2-9 PLL initial 2-8 PL0-PL20 bits 9-7 PL21-PL22 bits 9-7 PLL 1-11, 2-3 PLL capacitor signal 2-8 PLL initialize signal 2-9 PLL signals 2-7 PM0PM7 bits 7-11 Port A 2-3, 2-9 Port B 2-3, 2-4, 2-19, 5-3 port B 10 signal (PB10) 2-19 port B 11 signal (PB11) 2-20 port B 12 signal (PB12) 2-20 port B 13 signal (PB13) 2-21 port B 14 signal (PB14) 2-22 port B 15 signal (PB15) 2-23 port B 8 signal (PB8) 2-18 port B 9 signal (PB9) 2-19 port B signal (PB0PB7) 2-18 Port C 2-3, 2-4, 2-24, 2-25, 2-28, 5-3 port C 0 signal (PC0) 2-24 port C 1 signal (PC1) 2-25 port C 2 signal (PC2) 2-25 port C 3 signal (PC3) 2-26 port C 4 signal (PC4) 2-26 port C 5 signal (PC5) 2-27 Port C Control Register (PCRC) 7-43 Port C Data Register (PDRC) 7-45 Port C Direction Register (PRRC) 7-44 Port D 2-3, 2-4, 2-28, 5-4 port D 0 signal (PD0) 2-28 port D 1 signal (PD1) 2-28 port D 2 signal (PD2) 2-29 port D 3 signal (PD3) 2-30 port D 4 signal (PD4) 2-30 port D 5 signal (PD5) 2-31 Port D Control Register (PCRD) 7-43 Port D Data Register (PDRD) 7-45 Port D Direction Register (PRRD) 7-44 Port E 2-3, 2-32, 5-4 port E 0 signal (PE0) 2-32 port E 1 signal (PE1) 2-32 port E 2 signal (PE2) 2-33 Port E Control Register (PCRE) 8-27 Port E Data Register (PDRE) 8-28 Port E Direction Register (PRRE) 8-27 power 2-3, 2-5 ground 2-6 low 1-7 management 1-7 standby modes 1-7 power input address bus 2-5 bus control 2-5 data bus 2-5 ESSI 2-6 host interface 2-5 PLL 2-5 quiet 2-5 SCI 2-6 timer 2-6 PreDivider Factor bits (PD) 4-18 Prescale Modulus Select bits (PM0PM7) 7-11 Prescaler Counter 9-7 Prescaler Counter Value bits (PC0-PC20) 9-9 Prescaler Load Value bits (PL0-PL20) 9-7 Prescaler Range bit (PSR) 7-11 Prescaler Source bits (PL21-PL22) 9-7 Program Address Bus (PAB) 1-13 Program Address Generator (PAG) 1-10 Program Control Unit (PCU) 1-10 Program Counter register (PC) 1-10 Freescale Semiconductor, Inc... MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D I-9 Freescale Semiconductor, Inc. R Program Data Bus (PDB) 1-13 Program Decode Controller (PDC) 1-10 Program Interrupt Controller (PIC) 1-10 Program Memory Expansion Bus 1-13 program RAM 3-6 Programming Sheets N See Appendix B PRRC register 7-44 PRRD register 7-44 PRRE register 8-27 PSR bit 7-11 bits 515 6-10 in HPC register bit 7 6-14 in HSR register bits 515 6-11 in ICR register bit 6 6-24 in ISR register bit 5 6-27 bit 6 6-27 in OBCR register bits 1215 10-15 in OSCR register bit 5, bits 823 10-9 in TCSR register bits 3, 10, 14, 1619, 22, 23 9-15 in TPCR 9-9 in TPLR 9-8 RESET 2-14 reset signal 2-14 reverse-carry adder 1-9 RFS bit 7-28 RIE bit 7-26, 8-11 RLIE bit 7-27 ROE bit 7-29 ROM bootstrap 3-7 row address strobe signals RAS0RAS3 2-10 RREQ bit 6-23 RS0RS4 bits 10-5 RSMA, RSMB registers 7-35 RW00RW01 bits 10-12 RW10RW11 bits 10-13 RWU bit 8-9 RX register 7-33 RXD 2-32 RXD signal 8-4 RXDF bit 6-26 RXH, RXM, RXL registers 6-28 R Freescale Semiconductor, Inc... R/W bit 10-6 R8 bit 8-15 RAS0RAS3 signals 2-10 RCM bit 8-17 RD signal 2-10 RDF bit 7-30 RDRF bit 8-14 RE bit 7-26, 8-10 read enable signal (RD) 2-10 Read/Write Command bit (R/W) 10-6 Receive Byte Registers (RXH, RXM, RXL) 6-28 Receive Clock Mode Source bit (RCM) 8-17 Receive Data Register (RX) 7-33 Receive Data Register Full bit (RDF) 7-30 Receive Data Register Full bit (RDRF) 8-14 Receive Data Register Full bit (RXDF) 6-26 Receive Data signal (RXD) 8-4 Receive Exception Interrupt Enable bit (REIE) 7-27 Receive Frame Sync Flag bit (RFS) 7-28 receive host request signal (HRRQ/HRRQ) 2-23 Receive Interrupt Enable bit (RIE) 7-26, 8-11 Receive Last Slot Interrupt Enable bit (RLIE) 7-27 Receive Request Enable bit (RREQ) 6-23 Receive Shift Register 7-33 Receive Slot Mask Registers (RSMA, RSMB) 7-35 Received Bit 8 Address bit (R8) 8-15 Receiver Enable bit (RE) 8-10 Receiver Overrun Error Flag bit (ROE) 7-29 Receiver Wakeup Enable bit (SBK) 8-9 Register Select bits (RS0RS4) 10-5 REIE bit 7-27, 8-13 reserved bits in CRA register 7-11, 7-13, 7-14 in HBAR register bits 515 6-12 in HCR register S SAMPLE/PRELOAD instruction 11-9 SBK bit 8-9 SC register 1-11 SC0 signal 7-6, 7-8 SC00 signal 2-24 SC01 signal 2-25 SC02 signal 2-25 I-10 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. S SC1 signal 7-7 SC10 2-28 SC11 2-28 SC12 2-29 SCCR register 8-15 bits 011NClock Divider bits (CD0CD11) 8-16 bit 12NClock Out Divider bit (COD) 8-16 bit 13NSCI Clock Prescaler bit (SCP) 8-17 bit 14NReceive Clock Mode Source bit (RCM) 8-17 bit 15NTransmit Clock Source bit (TCM) 8-18 SCD0 bit 7-16 SCD1 bit 7-16 SCD2 bit 7-16 SCI 1-16, 2-4, 2-32 exceptions 8-26 Idle Line 8-26 Receive Data 8-26 Receive Data with Exception Status 8-26 Timer 8-26 Transmit Data 8-26 GPIO functionality 8-27 initialization 8-24 example 8-25 operating mode Asynchronous 8-21 Synchronous 8-21 operating modes Asynchronous 8-21 programming model 8-4 reset 8-22 state after reset 8-23 transmission priority preamble, break, and data 8-26 SCI (GPIO) 5-4 SCI Clock Control Register (SCCR) 8-15 SCI Clock Polarity bit (SCKP) 8-12 SCI Clock Prescaler bit (SCP) 8-17 SCI exceptions Receive Data 8-26 SCI pins RXD, TXD, SCLK 8-3 SCI Receive Register (SRX) 8-19 SCI Receive with Exception Interrupt bit (REIE) 8-13 SCI Serial Clock signal (SCLK) 8-4 SCI Shift Direction bit (SSFTD) 8-9 SCI Status Register (SSR) 8-13 SCI Transmit Register (STX) STX register 8-20 SCK signal 7-5 SCK0 2-26 SCK1 signal 2-30 SCKD bit 7-16 SCKP bit 8-12 SCLK signal 2-33, 8-4 SCP bit 8-17 SCR register bits 0-2NWord Select bits (WDS0-WDS2) 8-8 bit 3NSCI Shift Direction bit (SSFTD) 8-9 bit 4NSend Break bit (SBK) 8-9 bit 5NWakeup Mode Select bit (WAKE) 8-9 bit 6NReceiver Wakeup Enable bit (RWU) 8-9 bit 7NWired-OR Mode Select bit (WOMS) 8-10 bit 8NReceiver Enable bit (RE) 8-10 bit 9NTransmitter Enable bit (TE) 8-10 bit 10NIdle Line Interrupt Enable bit (ILIE) 8-11 bit 11NReceive Interrupt Enable bit (RIE) 8-11 bit 12NTransmit Interrupt Enable bit (TIE) 8-12 bit 13NTimer Interrupt Enable bit (TMIE) 8-12 bit 14NTimer Interrupt Rate bit (STIR) 8-12 bit 15NSCI Clock Polarity bit (SCKP) 8-12 bit 16NSCI Receive with Exception Interrupt Enable bit (REIE) 8-13 Select SC1 as Transmitter 0 Drive Enable bit (SSC1) 7-14 Send Break bit (SBK) 8-9 Serial Clock signal (SCK) 7-5 serial clock signal (SCK0) 2-26 serial clock signal (SCK1) 2-30 serial clock signal (SCLK) 2-33 Serial Communication Interface (SCI) 2-32 Serial Communications Interface (SCI) 1-16, 2-3, 8-3 Serial Control 0 Direction bit (SCD0) 7-16 serial control 0 signal (SC0) 7-6, 7-8 serial control 0 signal (SC00) 2-24 serial control 0 signal (SC10) 2-28 Serial Control 1 Direction bit (SCD1) 7-16 serial control 1 signal (SC01) 2-25 serial control 1 signal (SC1) 7-7 serial control 1 signal (SC11) 2-28 Serial Control 2 Direction bit (SCD2) 7-16 serial control 2 signal (SC02) 2-25 serial control 2 signal (SC12) 2-29 Serial Input Flag 0 bit (IF0) 7-28 Serial Input Flag 1 bit (IF1) 7-28 Serial Output Flag bits (OF0OF1) 7-15 Freescale Semiconductor, Inc... MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D I-11 Freescale Semiconductor, Inc. T serial protocol in OnCE module 10-22 serial receive data signal (RXD) 2-32 Serial Receive Data signal (SRD) 7-4 serial receive data signal (SRD0) 2-26 serial receive data signal (SRD1) 2-30 Serial Transmit Data signal (STD) 7-4 serial transmit data signal (STD0) 2-27 serial transmit data signal (STD1) 2-31 serial transmit data signal (TXD) 2-32 SHFD bit 7-17 Shift Direction bit (SHFD) 7-17 signal groupings 2-3 signals 2-3 functional grouping 2-4 Single Data Strobe 2-4 Sixteen-bit Compatibility 3-3 Size register (SZ) 1-10 Software Debug Occurrence bit (SWO) 10-8 SP 1-11 SR register 1-10 SRAM interfacing 1-13 SRD signal 7-4 SRD0 2-26 SRD1 2-30 SRX read as SRXL, SRXM, SRXH 8-19 SRX register 8-19 SS 1-11 SSC1 bit 7-14 SSFTD bit 8-9 SSISR register 7-27 bit 0NSerial Input Flag 0 bit (IF0) 7-28 bit 1NSerial Input Flag 1 bit (IF1) 7-28 bit 2NTransmit Frame Sync Flag bit (TFS) 7-28 bit 3NReceive Frame Sync Flag bit (RFS) 7-28 bit 4NTransmitter Underrun Error Flag bit (TUE) 7-29 bit 5NReceiver Overrun Error Flag bit (ROE) 7-29 bit 6NTransmit Data Register Empty bit (TDE) 7-29 bit 7NReceive Data Register Full bit (RDF) 7-30 SSR register 8-13 bit 1NTransmitter Empty bit (TRNE) 8-13 bit 2NReceive Data Register Full bit (RDRF) 8-14 bit 2NTransmit Data Register Empty bit (TDRE) 8-13 bit 3NIdle Line Flag bit (IDLE) 8-14 bit 4NOverrun Error Flag bit (OR) 8-14 bit 5NParity Error bit (PE) 8-14 bit 6NFraming Error Flag bit (FE) 8-15 bit 7NReceived Bit 8 Address bit (R8) 8-15 Stack Counter register (SC) 1-11 Stack Pointer (SP) 1-11 standby mode Stop 1-7 Wait 1-7 Status Register (SR) 1-10 STD signal 7-4 STD0 2-27 STD1 2-31 STIR bit 8-12 stop standby mode 1-7 STX register read as STXL, STXM. STXH, and STXA 8-20 SWO bit 10-8 SYN bit 7-18 System Stack (SS) 1-11 SZ register 1-10 Freescale Semiconductor, Inc... T TA signal 2-11 TAP 1-11 TAP controller 11-6 TC0TC3 bits 9-10 TCIE 9-10 TCK pin 11-5 TCK signal 2-35 TCM bit 8-18 TCR register 9-16 TCSR register 9-9 bit 0NTimer Enable bit (TE) 9-9 bits 47NTimer Control bits (TC0TC3) 9-10 bit 8NInverter bit (INV) 9-11 bit 13NData Output bit (DO) 9-14 reserved bitsNbits 3, 10, 14, 1619, 22, 23 9-15 TDE bit 7-29 TDI pin 11-5 TDI signal 2-35 TDO signal 2-36 TDRE bit 8-13 I-12 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. T TE bit 8-10, 9-9 TE0 bit 7-24 TE1 bit 7-23 TE2 bit 7-22 TEIE bit 7-27 Test Access Port (TAP) 1-11, 11-3 Test Clock Input pin (TCK) 11-5 Test Data Input pin (TDI) 11-5 Test Mode Select Input pin (TMS) 11-5 Test Reset Input pin (TRST) 11-5 TFS bit 7-28 TIE bit 7-26, 8-12 Time Slot Register (TSR) 7-34 timer special cases 9-27 Timer (GPIO) 5-4 timer 0 signal (TIO0) 2-34 timer 1 signal (TIO1) 2-34 timer 2 signal (TIO2) 2-35 Timer Control bits (TC0TC3) 9-10 Timer Control/Status Register (TCSR) 9-9 Timer Count Register (TCR) 9-16 Timer Enable bit (TE) 9-9 Timer Interrupt Enable bit (TMIE) 8-12 Timer Interrupt Rate bit (STIR) 8-12 timer mode mode 0NGPIO 9-17 mode 1Ntimer pulse 9-18 mode 2Ntimer toggle 9-19 mode 3Ntimer event counter 9-20 mode 4Nmeasurement input width 9-21 mode 5Nmeasurement input period 9-22 mode 6Nmeasurement capture 9-23 mode 7Npulse width modulation 9-24 mode 8Nreserved 9-25 mode 9Nwatchdog pulse 9-25 mode 10Nmeasurement toggle 9-26 modes 1115Nreserved 9-27 Timer module 1-17, 2-34 architecture 9-3 programming model 9-5 timer block diagram 9-4 Timer Prescaler Count Register (TPCR) 9-8 Timer Prescaler Load Register (TPLR) 9-7 Timers 2-3, 2-4 TLIE bit 7-26 TME bit 10-8 TMIE bit 8-12 TMS pin 11-5 TMS signal 2-36 TO bit 10-9 TOIE 9-9 TPCR register 9-8 bits 0-20NPrescaler Counter Value bits (PC0-PC20) 9-9 bit 21-23Nreserved bits 9-9 reserved bitsNbits 21-23 9-9 TPLR register 9-7 bits 0-20NPrescaler Load Value bits (PL0-PL20) 9-7 bits 21-22NPrescaler Source bits (PL0-PL20) 9-7 bit 23Nreserved bit 9-8 reserved bitNbit 23 9-8 Trace buffer 10-21 Trace mode enabling 10-18 in OnCE module 10-15 Trace Mode Enable bit (TME) 10-8 Trace Occurrence bit (TO) 10-9 transfer acknowledge signal 2-11 Transmit 0 Enable bit (TE0) 7-24 Transmit 1 Enable bit (TE1) 7-23 Transmit 2 Enable bit (TE2) 7-22 Transmit Byte Registers (TXH, TXM, TXL) 6-29 Transmit Clock Source bit (TCM) 8-18 Transmit Data Register Empty bit (TDE) 7-29 Transmit Data Register Empty bit (TDRE) 8-13 Transmit Data Register Empty bit (TXDE) 6-27 Transmit Data signal (TXD) 8-4 Transmit Exception Interrupt Enable bit (TEIE) 7-27 Transmit Frame Sync Flag bit (TFS) 7-28 transmit host request signal (HTRQ/HTRQ) 2-22 Transmit Interrupt Enable bit (TIE) 7-26, 8-12 Transmit Last Slot Interrupt Enable bit (TLIE) 7-26 Transmit Request Enable bit (TREQ) 6-23 Transmit Shift Registers 7-33 Transmit Slot Mask Registers (TSMA, TSMB) 7-34 Transmitter Empty bit (TRNE) 8-13 Transmitter Enable bit (TE) 8-10 Transmitter Ready bit (TRDY) 6-27 Transmitter Underrun Error Flag bit (TUE) 7-29 TRDY bit 6-27 TREQ bit 6-23 triple timer module 1-17 TRNE bit 8-13 TRST pin 11-5 TSMA, TSMB registers 7-34 TSR register 7-34 TUE bit 7-29 TX2, TX1, TX0 registers 7-34 Freescale Semiconductor, Inc... MOTOROLA For More Information On This Product, Go to: www.freescale.com DSP56309UM/D I-13 Freescale Semiconductor, Inc. V TXD signal 2-32, 8-4 TXDE bit 6-27 TXH, TXM, TXL registers 6-29 V VBA register 1-10 Vector Base Address register (VBA) 1-10 W wait standby mode 1-7 WAKE bit 8-9 Wakeup Mode Select bit (WAKE) 8-9 WDS0-WDS2 bits 8-8 weak keeper 2-24, 2-25, 2-26, 2-27, 2-28, 2-29, 2-30, 2-31, 2-32, 2-33, 2-34, 2-35 Wired-OR Select bit (WOMS) 8-10 WL0WL1 bits 7-14 WOMS bit 8-10 Word Length Control bits (WL0WL1) 7-14 Word Select bits (WDS0-WDS2) 8-8 WR signal 2-10 write enable signal 2-10 Freescale Semiconductor, Inc... X X data RAM 3-6 X Memory Address Bus (XAB) 1-13 X Memory Data Bus (XDB) 1-13 X Memory Expansion Bus 1-13 XAB 1-13 XDB 1-13 XTAL 2-8 XTAL Disable bit (XTLD) 4-18 XTLD bit 4-18 Y Y data RAM 3-7 Y Memory Address Bus (YAB) 1-13 Y Memory Data Bus (YDB) 1-13 Y Memory Expansion Bus 1-13 YAB 1-13 YDB 1-13 I-14 For More Information On This Product, Go to: www.freescale.com DSP56309UM/D MOTOROLA Freescale Semiconductor, Inc. 1 2 3 4 DSP56309 OVERVIEW SIGNAL/CONNECTION DESCRIPTIONS MEMORY CONFIGURATION CORE CONFIGURATION GENERAL PURPOSE I/O HOST INTERFACE (HI08) ENHANCED SYNCHRONOUS SERIAL INTERFACE SERIAL COMMUNICATION INTERFACE (SCI) TIMER MODULE ON-CHIP EMULATION MODULE JTAG PORT BOOTSTRAP PROGRAM EQUATES BSDL LISTING PROGRAMMING REFERENCE INDEX For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... 5 6 7 8 9 10 11 A B C D I Freescale Semiconductor, Inc. DSP56309 OVERVIEW SIGNAL/CONNECTION DESCRIPTIONS MEMORY CONFIGURATION CORE CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 A B C D I Freescale Semiconductor, Inc... GENERAL PURPOSE I/O HOST INTERFACE (HI08) ENHANCED SYNCHRONOUS SERIAL INTERFACE SERIAL COMMUNICATION INTERFACE (SCI) TIMER MODULE ON-CHIP EMULATION MODULE JTAG PORT BOOTSTRAP PROGRAM EQUATES BSDL LISTING PROGRAMMING REFERENCE INDEX For More Information On This Product, Go to: www.freescale.com |
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